標題: 具立體通道之矽奈米級金氧半場效應電晶體本質參數擾動之研究
Intrinsic Parameter Fluctuation in Nanoscale MOSFET with Vertical Silicon Channels
作者: 黃至鴻
Hwang, Chih-Hong
李義明
Li, Yiming
電信工程研究所
關鍵字: 本質參數擾動;奈米級電晶體;多閘極電晶體;模擬;Intrinsic Parameter Fluctuation;Nanoscale Transistor;Vertical Channel Transistor;Modeling
公開日期: 2009
摘要: 延續摩爾定律而獲得高性能矽晶片以及高密度元件之觀點,新材料、新製程與新結構的開發是半導體製造上繼續微縮元件的尺寸最有效的策略方案;其中,16 奈米之後電晶體結構的改變儼然已成為非常前瞻與重要的趨勢,因此研究隨機摻雜問題與製程變異在多重閘極場效電晶體特性之影響已為重要且急迫之課題之一。因此本論文發展了三維度元件電路模擬技術使用等效原子層級離散摻雜暨量子傳輸方程的大尺度統計運算方法,並成功地分析16 奈米立體矽場效應電晶體特性之擾動由單閘極、雙閘極、三閘極至全閘極電晶體。此研究方法之準確度已成功地以次20 奈米矽場效應電晶體特性之實驗驗證。相較於單閘極電晶體,臨界電壓擾動在雙閘極、三閘極至全閘極分別被壓抑2.2、3.3 與4 倍,壓抑的原理及物理特性均有探討。此外,近來金屬閘極與高介電係數材料的使用已成為奈米電晶體元件開發之重要課題,但金屬閘極的使用將因金屬材料本身結晶顆粒的大小與方向帶來另外的擾動來源,因此本論文發展蒙地卡羅方法廣泛的分析閘極功函數擾動、離散摻雜擾動與製程變異在多重閘極場效電晶體特性暨其電路之影響,發現閘極功函數擾動對於金屬閘極電晶體尤其是p-type 元件之重大影響,此論文結果對於電晶體擾動壓抑之推估以及下世代電晶體特性擾動分析極有助益。
Gate-length scaling is still the most effective way to continue Moore’s Law for transistor density increase and chip performance enhancement. Accompanied with complementary metal-oxide-semiconductor (CMOS) technology advanced to 45-nm node in production, further scaling down to sub-20 nm and even beyond has been widely noticed encountering much more challenges at short channel control than previous generations. The worsened short channel control of nanoscale transistor not only increases standby power dissipation, but also enlarges electrical characteristic fluctuations, such as the deviation of threshold voltage, drive current, mismatch, and so on. The fluctuation budget has to be controlled even tighter due to doubly increased transistor number along with technology node moving ahead. Moreover, the fluctuation is intrinsically increased with the scaling of transistor feature size, even not considering worsened short channel control. This thesis describes the intrinsic parameter fluctuations in vertical-channel devices from planar transistor to double gate, tri-gate, omega fin-type field effect transistors (FinFETs) and nanowire FinFETs through experimental validated three-dimension device simulation and characterization. The implications of device variability in nanoscale transistor circuits are advanced. The extensive study assesses the fluctuations on device and circuit reliability, which can in turn be used to optimize nanoscale MOSFET and circuits. Full realization of the benefit of nanoscale transistor therefore requires development and optimization of new device materials, structures, and technologies to keep transistor performance and reliability.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009213804
http://hdl.handle.net/11536/70867
Appears in Collections:Thesis