標題: 基於一百奈米製程之具區塊層級最佳化的複合式溫度感應功率管理系統
A Comprehensive Thermal-Aware Power Management System with Block-Level Optimization in 100nm CMOS Technology
作者: 詹偉閔
Wei-Min Chan
闕河鳴
Herming Chiueh
電信工程研究所
關鍵字: 溫度;感應;功率;管理;Thermal;Aware;Power;Management
公開日期: 2005
摘要:   由於電池壽命有限的緣故,現今的單晶片整合與手攜式系統強調低功率技術的應用。傳統的功率管理設計主要是針對動態功率損耗的降低,而最近的設計則開始將靜態功率損耗納入考量,因為在奈米製程下漏電流逐漸成為不可忽略的要素。最新的研究善用了單晶片設計思維的模組化特性,發展出區塊層級的控制技術來降低功率損耗,然而區塊之間的溫差對於單晶片系統設計所帶來的影響卻鮮少被討論。職是之故,本論文提出了複合式熱感應功率管理及其區塊層級的最佳化。所提出的設計應用了多種低功率技術來控制晶片內不同的功率損耗來源,同時顧及溫差所帶來的影響以維持各區塊間效能的一致性。模擬結果顯示,本設計對於電路的穩定性有顯著的提升,而對於漏電流也得到有效的鉗制。此模擬結果基於台積電一百奈米互補式金氧半導體製程。
Modern SoC integrations and mobile systems have emphasized low power techniques due to shortage of battery life. Conventional power management designs focused on the reduction of dynamic power consumption, recent designs begin to take leakage power into consideration since it becomes an important factor in nano-scale CMOS technology. Latest development has taken advantage of modularity in SoC design methodology to develop the block-level control technique for power reductions. However, thermal gradient over the system and its impacts to SoC designs are barely discussed. In this thesis, a block-level optimization of comprehensive thermal aware power management is presented. The proposed design applies several low power techniques to control different power sources and handles thermal impacts to provide performance coherence. As a result, optimal power reductions and performance coherence can be guaranteed within the whole system. The simulation results show a significant improvement in stability and leakage power reduction for most circuitries. These results are based on TSMC 100nm CMOS technology.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009213641
http://hdl.handle.net/11536/70812
顯示於類別:畢業論文


文件中的檔案:

  1. 364101.pdf