Design and Analysis of Cellular Nonlinear Networks with Ratio Memory or Large-Neighborhood and their Applications
|關鍵字:||細胞非線性網路;比例式記憶細胞非線性網路;聯想記憶體;細胞非線性網路通用機器;大鄰近層細胞非線性網路;Cellular nonlinear network;Ratio-memory cllular nonlinear network;Associative memory;Cellular nonlinear network universal machine;Large-neighborhood cellular nonlinear network|
|摘要:||本論文的主旨在於闡述細胞非線性網路架構之分析與設計及其在聯想式記憶體及圖像辨識上之應用。論文中包含下列三個主要部分: (1) 以雙載子接面電晶體乘除法器架構之比例式記憶細胞非線性網路之分析與設計; (2)含自我回授之鍵值之新型細胞化非線性網路的設計; (3)大鄰近層細胞非線性網路通用機器之概念設計。
In this thesis the new analog cellular nonlinear(neural) network structure with ratio memory and the cellular nonlinear(neural) network universal machine are designed and analyzed. The main parts of this thesis include: (1) the analysis and design of the cellular nonlinear(neural) network with ratio memory structure and the applied to the implementation of the analog associative memory; (2) the design of new ratio memory cellular nonlinear(neural) networks structure with self-feedback weight of template A; (3) the conceptual design of the new Cellular Nonlinear(Neural) Network Universal Machine with programmable large-neighborhood asymmetric templates. Firstly, the new elements, called analog current mode four-quadrant multiplier and two quadrant divider, which is applied in the ratio memory cellular nonlinear(neural) network for the compact implementation of VLSI neural network is proposed and analyzed. In the new element structure, the parasitic PNP Bipolar Junction Transistor (BJT) in the CMOS process is used to implement the multiplication and division. It utilizes the exponential relationship between the emitter current and the base-emitter voltage of parasitic PNP Bipolar Junction Transistor (BJT). Using this relation, both multiplication and division can be realized in a simple BJT structure. The BJT-based multiplier-divider has the advantages of compact structure and small chip size. The BJT-based multiplier-divider has been successfully applied to the implementation of the analog associative memory. The analog associative memory can store many sets of exemplar patterns. Moreover, the input patterns can be recognized and recovered to the correct patterns. An experimental chip of the proposed neuron-bipolar junction transistor (□BJT) analog associative memory with the cell size of 9x9 has been designed and fabricated by using 0.35 µm single-poly quadric-metal (SPQM) n-well CMOS technology. The analog associative memory has been successfully verified through both simulation and measurement in the ratio memory cellular nonlinear(neural) network with the sizes of 9x9. With simple and compact structure and high integration capability, the proposed BJT-based multiplier-divider has a great potential in the VLSI implementation of neural network. Secondly, based on the basic ratio memory cellular nonlinear(neural) network for associative memory, a new ratio memory cellular nonlinear(neural) networks (RMCNN) structure called the SRMCNN are proposed and analyzed. In the new RMCNN, the self-feedback weight of template A is applied for enlarge the numbers of stored patterns. Except the above additional templates, the learning algorithm is also a little different from the original RMCNN. In the new RMCNN, the denominator of the ratio weight is simplified to be the maximum absolute value of the absolute weight instead of the sum of the absolute value of the absolute weights. Thus, the sum circuit can be eliminated. Though the learned weights of the new RMCNN is different from the original RMCNN, the software simulation results display that the new RMCNN still keep feature enhancement. Furthermore, the new RMCNN can recognize and recover more patterns than the original RMCNN. The new RMCNN can learn up to 98 patterns. In the case of noise variance level being 0.3, the recovery rates of the new RMCNN is still up to 86.9%. Finally, the new cellular nonlinear(neural) network universal machine (CNNUM) structure with asymmetric templates and large-neighborhood is proposed and analyzed. In conventional CNNUM, only the single-neighboring cells are connected to the cell. It is because that the 2D CMOS technology limits the implementation of large-neighboring or complicated interconnections. Indirect connection used in the LN-CNN makes it being possible to implement the large-neighborhood templates without extra direct large-neighboring interconnections. As the demonstrative examples on the applications of the proposed large-neighborhood CNN, three functions of noise removal, connected component detection, and Muller-Lyer arrowhead illusion have been successfully realized and verified by software simulation with the corresponding templates. From the above results, it is believed that the proposed RMCNN structure and its application on pattern recognition have a great potential in system-on-a-chip design of the neural network systems, and the proposed LN-CNNUM structure can simplify the complex of the large-neighborhood interconnections. Further researches in the two fields will be conducted in the future, and the ratio memory structure will be embedded into the analog parallel image processor.