LPGC: A Novel Low Power Driven Placement Algorithm Based on Optimal Gated Clock Topology
Simon Yi-Hung Chen
In this thesis, a placer based on optimizing the power consumption of clock gating network is presented. First, we construct an optimal gated clock topology based on considering the physical connectivity, and minimizing the total switching activity of the clock network. Then, with a novel measure function, our placer can build a suitable placement solution which makes the optimal gated clock topology being routable. Our placer can give a dedicated placement seed to any low power gated clock routing algorithm since we provide them a global optimized solution for reducing the interconnect power which is a severe factor in the coming nano-scale era. Experimental results show that our placer indeed works and can help gated clock routing algorithms to additionally save power consumption by 25%.
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