標題: 10位元80百萬赫茲導管式類比數位轉換器和CMOS能階參考電路
10-Bit 80MHz Pipelined Analog-to-Digital Converter and CMOS Bandgap Reference Circuit
作者: 張家瑋
Chia-Wei Chang
洪崇智
Chung-Chih Hung
電信工程研究所
關鍵字: 導管式;轉換器;能階;Pipelined;Converter;Bandgap
公開日期: 2005
摘要: 高速類比數位轉換器是目前高效能系統,例如光纖通訊的前端接收器和資料通訊連結系統中不可獲缺的主要電路。高速類比數位轉換器在設計上,需要考慮如何將電路不匹配所造成的靜態(static)或動態(dynamic)的誤差如DNL,INL等誤差降低,以增加電路的解析度(resolutions)。此高速類比數位轉換器亦將採用低電壓操作,已達到低功率消耗的標準。在設計上如何將高速,高解析度和低功率消耗的優點集中在此類比數位轉換器,將是研究的重點之ㄧ。 一般而言,類比數位轉換器取樣頻率大於1 GS/s時,大多採用 Flash架構的轉換器。當解析度每增加1位元(Bit)時,電晶體的數目將增加4~8倍,造成晶片面積和功率消耗增加,因此一般而言採用Flash架構的轉換器,其解析度普遍都不會大於6位元。為了提高轉換器的解析度,可採用導管式(Pipeline)架構的轉換器,此導管式轉換器主要是犧牲整體速度達到解析度的提升,因此可在速度、解析度和晶片面積之間取得最佳化。解析度10位元、取樣頻率80 MS/s的導管式類比數位轉換器(Pipelined ADC)將會在此研究中實現。 在此研究中,轉換器採用每一級1.5位元,串接八級,最後加上一級2位元的子轉換器,實現10位元的解析度。一個10位元每秒取樣80百萬次操作電壓1.8伏特的導管式類比數位轉換器,在晶片中心(CIC)提供的台積電(tsmc)標準0.18微米製程中被設計與實現。 論文中,低功率消耗的互補式金氧半能階參考電路(CMOS Bandgap Reference),將以晶片中心(CIC)提供的台積電(tsmc)標準0.18微米製程設計與實現。此電路將電晶體偏壓在弱反轉層(weak-inversion region),使其產生取代傳統雙載子(BJT)元件的電壓-電流關係式。此電路利用偏壓在弱反轉層電晶體閘源極(VGS)間的壓差,產生正溫度係數的電壓,再加上負溫度係數的電壓,藉此達到穩壓的效果。此電路以標準的CMOS製程實現,不需而外的製程輔助。
High speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are very significant blocks of nowadays high-performance systems such as data communication links using multilevel signaling (e.g., PAM and QAM). The main issues in the design of high-speed ADCs include static and dynamic offset reduction, low supply-voltage operation, gain, and speed optimization. Design tradeoffs between power, speed, and chip area further tighten the design requirements. For analog to digital conversion at sampling rates above 1 GS/s, typically flash converters are used. The resolution of these converters is limited because each extra bit would require 4 to 8 times more gate areas resulting in excessive power consumption. Generally speaking, flash converters are practically limited to 6 bits of accuracy. For lower speed, alternative architectures are widely available, such as pipelined converters which enable higher resolution and higher efficiency. In this research, a 10-bit 80 MS/s pipelined ADC will be presented. The converter uses the 1.5 bit/stage architecture that cascodes eight stages. A 2 bit flash sub-converter in the last stage is utilized to achieve the 10-bit resolution. A 10 bits、80 MS/s and 1.8 V Pipelined ADC was designed and implemented by tsmc 0.18um process supported by CIC. Also, a low power CMOS Bandgap Reference Circuit was designed and implemented by tsmc 0.18um process supported by CIC. The BJTs are replaced by the MOSFETs which operate in the weak-inversion region because the MOSFETs operating in the weak-inversion region have similar voltage-current relationship to the BJTs. The bandgap reference circuit uses the different VGS voltage between two MOSFETs operated in weak-inversion region to generate the voltage of positive temperature coefficient. We could get the stable reference voltage by combine the voltage of positive temperature coefficient with voltage of negative temperature coefficient. This circuit was designed in standard CMOS process without any other process.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009213604
http://hdl.handle.net/11536/70457
Appears in Collections:Thesis


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