標題: 多媒體串列處理器之分散式記憶體管理單元設計
Distributed Memory Management Unit Design for Media Stream Processor Architecture
作者: 鄭漳源
Chang-Yuan Cheng
闕河鳴
Herming Chiueh
電信工程研究所
關鍵字: 多媒體;串列處理器;分散式記憶體;記憶體管理;Media;Stream Processor;Distributed Memory;Memory Management
公開日期: 2005
摘要: 在現今多媒體應用上,影像處理、視訊壓縮、二維和三維繪圖、資料複製和資料搬移是常見的程序。然而,處理器和記憶體之間的頻寬差距造成傳輸資料減速。為了縮短現今多媒體影像處理架構上的差距,這篇論文提出了一個分散式記憶體管理單元。分散式記憶體管理單元包含位址轉換單元和雙倍資料率記憶體控制器。位址轉換單元提供一個虛擬記憶體機制和用來節省資料傳輸時間。雙倍資料率記憶體控制器用於簡易地爆發讀取和寫入模式。從分散式記憶體管理單元實現的結果顯示,當傳送十六百萬位元組資料量時,提出的位址轉換單元架構比傳統的位址轉換單元速度提升了二百萬倍。然而,當資料量小於十六百萬位元組時,無位址轉換單元傳輸時間與有位址轉換單元傳輸時間相比會隨著資料量的增加而增加。本篇論文便是針對現今多媒體應用架構中,用微量增加的電路面積和功率消耗以換取資料傳輸效能的躍進。
In modern multimedia applications such as image processing, video compression, two-dimension and three-dimension graphics, data copying and data moving are common processes. However, the bandwidth gaps between processors and memory cause the slow down of transition data. In order to bridge the gap, this thesis proposed a distributed memory management unit (DMMU) for modern media processing architectures. The DMMU consists of address translation unit (ATU) and double data rate (DDR) memory controller. The ATU provides a virtual memory mechanism, and been used to save data transition time. The DDR memory controller is used in simply burst read and burst write mode. The result of DMMU implementation shows that proposed ATU architecture provides 2 million times speed-up than conventional ATU when transmitted 16MB data size. However, when the data capacity is less than 16MB, the proportion of the transition time without ATU/ ATU is increased for the data capacity. The proposed design provides a leap up in data transition for modern media processing architecture with a tiny overhead in circuit area and power.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009213603
http://hdl.handle.net/11536/70446
Appears in Collections:Thesis