Study of Deep Depletion Phenomena in SrTiO3 High-k Gate Oxide and Its Application on the Ferroelectric Memory
T. Y. Tseng
|關鍵字:||高介電閘極氧化層;鈦酸鍶;鐵電記憶體;載子生命期;High-k gate oxide;STO;Ferroelectric memory;Carrier lifetime|
|摘要:||本論文是使用物理氧相交流濺鍍法分別在氬氣-氧氣或氬氣-氮氣氣氛中，在p型矽基板上成長高介電鈣鈦礦結構的鈦酸鍶薄膜，且製備成金屬-絶緣體-半導體 (MIS) 結構作電性分析。其中除了探討在不同混合氣氛中濺鍍鈦酸鍶薄膜對其電容-電壓和漏電流特性之影響，且深入研究因其漏電流所引發之深空乏現象。當在負偏壓時，我們證明其漏電流主控機制在低電場為Schottky 放射機制而在高電場為 Fowler– Nordheim 穿透機制。而在正徧壓時，因為過大之漏電流造成反轉層之載子不足，使其漏電流趨於飽合且由於電中性原理造成空乏層寛度漸深。而深空乏現象的發生，會造成在高頻的電容-電壓量測上，強反轉區間之電容不再是一個不變值，而是會隨電壓遞減之函數，其函數型式可以由空乏層電容之公式來描述，並由其中求出矽基板之摻雜濃度。我們也進一步研究漏電流與深空乏層之關係並從關係式去淬取出載子的生命期。
最後我們應用鈦酸鍶薄膜當鐵電電晶體之絶緣層去製造金屬-鐵電膜-金屬-絶緣層-矽基板 與 金屬-鐵電膜-絶緣層-矽基板兩種結構並分析其特性。|
SrTiO3 thin films were deposited on p-type silicon substrate by radio-frequency (rf) magnetron sputtering in an Ar-O2 and Ar-N2 mixed ambient to form metal/insulator/semiconductor (MIS) structure. We found that the Schottky emission and Fowler-Nordheim tunneling were responsible for the leakage mechanics in the low and high electrical field under negative bias voltage, respectively. On the other hand, it is also demonstrated that the generation current dominated the leakage mechanics in the high electrical field of the positive bias voltage due to the high leaky insulator and the lack of electrons. To provide more electrons to maintain the leakage current in the higher electric field, the depletion width would be broadened to generate more electrons, as was called deep depletion. Therefore, the deep depletion was induced by high leakage current of the positive bias voltage. We also investigated the correlation between the deep depletion and the leakage mechanics of the positive bias voltage for STO gate dielectric capacitor. From the correlation between the deep depletion and the leakage mechanics, the generation lifetime of silicon substrate can be extracted. The extracted generation lifetime can be used to examine the quality of silicon substrates under different processing conditions. Finally, we used the STO as the Insulator layer for FeFETs. Pt/SBT/SRO/STO/Si (MFMIS) structures and Pt/SBT/STO/Si (MFIS) have been fabricated and characterized. Ferroelectric SBT films fabricated using the MOD technique annealed at 700˚C showed electrical properties with a remanent polarization 2Pr of 16.707μC/cm2 and coercive field 2Ec of 106 kV/cm. It was found that in MFMIS structures the memory window depended on the area ratio. When the area ratio is 16, a memory window as large as 3V was obtained for a voltage sweep of 3V.