Design of Low Jitter Frequency Synthesizers with Fast Frequency Acquisition Phase-Frequency Detector
|關鍵字:||鎖相迴路;低抖動;相位頻率偵測器;PLL;Low jitter;Phase-Frequency Detector|
為克服這些問題，本篇論文的研究焦點著重於相位頻率偵測器的設計。找尋且發展一個新的方法來消除死區和盲區。藉此，提出一個新型的相位頻率偵測器。最後，結合我們所提出的相位頻率偵測器，我們利用台灣積體電路 0.18-μm CMOS 製程來實現一個操作在 2.36~2.95-GHz 的整數除頻頻率合成器。模擬結果顯示，從 2.36 GHz 震盪頻率跳頻鎖定至 2.8 GHz 的情況下，本頻率合成器在1.8伏特的電壓供應下所消耗的功率為 25.9mW，其鎖定時間為1.93μs，相較於原始的頻率合成器改善了將近25%。|
In the world of modern wireless communication, phase-locked loop (PLL) based frequency synthesizers have played an important role in RF front-ends. As the wireless standards evolve, it presents an increasing challenge to meet the stringent requirements of low jitter or phase noise, fast settling time, and low power in PLL designs, which involve a lot of design issues and trade-offs. Two crucial design issues, dead-zone and blind-zone are detrimental to the performance of PLLs, increasing the timing jitter and slowing the settling speed, respectively. In particular, the decrease of one of them may cause the increase of the other. To overcome these issues, the research described in this thesis focuses on the design of phase-frequency detectors (PFDs). A new way to eliminate the dead-zone as well as the blind-zone has been founded and developed, whereby a novel and robust fast frequency-acquisition PFD is proposed. A 2.36~2.95-GHz integer-N frequency synthesizer including our proposed PFD is implemented in a standard TSMC 0.18-μm CMOS process. Simulation results reveal that the frequency synthesizer using our proposed PFD shows a locking time of 1.93μs, which is an improvement of up to 25% over that using a conventional PFD, while consuming 25.9mW at a 1.8V supply in the case of starting at 2.36 GHz and locking at 2.8 GHz. In addition, as compared with other PFD architectures, our proposed PFD manifests itself as a robust design for higher operating frequency, and neither dead-zone nor blind-zone.
|Appears in Collections:||Thesis|
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