標題: 應用於Serial ATA II 之1V 3GHz 展頻時脈產生器
A 1V 3GHz Spread Spectrum Clock Generator for Serial ATA II
作者: 莊誌倫
Chih-Lun Chuang
洪崇智
Chung-Chih Hung
電信工程研究所
關鍵字: 鎖相迴路;串行ATA;電磁干擾;展頻時脈產生器;PLL;Serial ATA;EMI;SSCG
公開日期: 2005
摘要: 高速電子儀器所產生的高頻電磁雜訊干擾(Electro-Magnetic Interference, EMI)常常會影響到其他電路的運作。傳統的解決方法是將電磁雜訊干擾加以屏蔽,或是控制時脈信號的上升速度,但是缺點是昂貴的成本與龐大的體積。現代的解決方法是直接在晶片上降低電磁雜訊干擾,以達到低成本與高彈性空間。 改變時脈信號的中心頻率是最常被採用的方法。這種方法被稱為展頻時脈技術(Spread Spectrum Clocking),因為時脈信號的頻譜被展開成較寬的頻帶。然而,由於除數上的規律性,造成了頻譜上明顯的突波。因此,在這本論文中,我們使用了高階的ΣΔ調變器來打散除法器除數的規律性,並將雜訊移往更高的頻帶。最後,我們可利用鎖相迴路閉迴路的特性將高頻的雜訊濾除。 將互補式金氧半製程的鎖相迴路應用於低電壓,高頻率之系統中是另外一項困難的任務。然而,隨著製程進步,電晶體越做越小,低電壓已經是一項必須面臨的驅勢。對於系統晶片整合(System-On-a-Chip, SOC)而言,類比電路必須與數位電路整合在同一晶片。因此,將類比電路操作在與數位電路同樣的低電壓下更是重要的。我們也提出了一個應用於第二代SATA系統之展頻時脈產生器。經由模擬驗證,可從3GHz向下展頻5000ppm,並且提供超過14dB的訊號振幅衰減量。
Electronic equipments often generate Electric-Magnetic Interference (EMI) that affects the operation of other equipments. In a portable device, the high-speed interfaces between peripheral storages and the other signal processing units are the main noise sources. The conventional techniques to reduce EMI tend to enclose or reduce the amount of the generated radiation, such as shield cables and coaxial wires, but are usually costly and bulky. Modern EMI reduction is done on-chip without using heavy shielding materials to the goal of low-cost and flexibility. Altering the center frequency of internal clocks is a widely adopted EMI reduction technique. The technique is called Spread Spectrum Clocking (SSC) because the spectrum of the clock is spread over a broader range. Serial ATA (SATA) specification defines an EMI reduction method using SSC. Several papers have discussed the EMI reduction using SSC [1][2]. However, because of the non-random and regular sequence of the divider modulus, the unwanted spur is obvious in the frequency spectrum of the clock. Therefore, in this thesis, we use a higher-order □□ modulator to randomize the divider modulus and remove the spur to high frequency. In the end, we can also filter out the unwanted noise with the closed loop behavior of the PLL. The application of CMOS PLL in low voltage and high frequency is crucial. With the reduction of the device feature size, a low supply voltage is a basic requirement. For System-On-a-Chip (SOC) design, analog circuits are necessary to be integrated with digital circuits. Therefore, it is significant for analog circuits to operate at the same low supply voltage as digital circuits. Here, we propose a 1V CMOS SSCG for 2nd generation Serial ATA. The SSCG achieves down spread 5000ppm from 3GHz while providing more than 14dB of power attenuation.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009213593
http://hdl.handle.net/11536/70357
Appears in Collections:Thesis


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