The Construction of Master Production Planning System for Memory IC Final Testing Factories
|關鍵字:||最終測試;製程規格能力;生產排程;final testing;process capability;production scheduling|
This research consider the construction of master production planning system for the memory IC final testing process in wafer fabrication, which includes such properties as make-to-order OEM services, multiple-priority orders, reentrant flow in final testing process, sequence dependent setup time, and batch operation. The most important performance criteria for IC final testing factories relates to customer satisfaction, which is measured by the on- time delivery of orders. Consequently, this research aims to construct a master production planning system with the minimization of the number of delay orders. The construction of master production planning system consists of three phases. First, according to the order demands in the planning horizon and the rule of balanced capacity loading, a linear programming model, developed in this research, is used to allocate the capacity of workstations to products. Second, based on the queuing theory and the allocation results in the first phase, estimates the production cycle time for all product type in all priorities. Furthermore, the estimated production cycle time will be regarded as the internal delivery due-date of lots. Finally, considering the priority of each lot and the capacity loading status of workstations, and according to constant WIP releasing, selects suitable releasing rules or dispatching rules in the shop floor. The rough-cut capacity planning (RCCP) developed in the first phase balances the capacity loading of workstations. The master production planning (MPS) developed in the second phase determines the estimation of product cycle time. The three phases master production planning system generates a production schedule. The simulation results show that the three phases master production planning system performs well in the criteria of on- time delivery ratio.