標題: 電子產品壽命與製作時程績效之評估
Assessing the Performance for the Lifetime and Processing time of Electronic Products
作者: 陳細鈿
Hsi-Tien Chen
唐麗英
Lee-Ing Tong
工業工程與管理學系
關鍵字: 製程能力指標;壽命績效指標;信賴下限;製程合格率;常態分配;指數分配;製作時程績效指標;成品交期績效指標;Process capability index;Lifetime performance index;Lower confidence limit;Conforming rate;Normal distribution;Exponential distribution;Processing time;Delivery time.
公開日期: 2002
摘要: 如何提昇產品的品質(包含可靠度、壽命、合格率,…,等)及有效地縮短交期,提高市場佔有率和經濟利益,越來越受到許多高科技廠商的重視。一些有關品質績效的評估方法已被提出,其中製程能力指標(process capability indices; PCIs)就是一個無單位、有效且方便的產品品質績效評估工具。探討PCIs的文獻固然多,但以往研究的主體多屬物理方面的品質特性,鮮少有感官的和時間導向的品質特性,而產品的感官品質特性又較為模糊而難以量化,因此本論文將探討時間導向的產品品質特性之製程績效評估,並以電子零件壽命為例介紹之。此外交期的長短亦是贏得訂單與否的重要因素,然而有關PCIs應用在產品製作時程與成品交期績效之評估方法並不多見,故本論文接著會以超大型積體電路為例,探討PCIs在製作時程及成品交期績效評估上的應用。因此,本論文之研究主題有二:第一個主題是以電子零件產品壽命為例,在指數分配的假設下,探討時間導向的產品品質特性之製程能力指標(或壽命績效指標),及其相對應之產品合格率間的關係,進而提供壽命績效指標與合格率間之對照表。此外,本研究在供應商生產製程為穩定的狀態下抽樣,構建出真實壽命績效指標之信賴下限,用以推斷電子產品壽命水準是否達到規格的要求,並供廠商用於分析改善其產品之製程能力,甚至挑選供應商之用。第二個主題是以超大型積體電路(Very Large Scale Integration; VLSI)為例,在VLSI各階段或步驟之製作時程與成品交期為常態分配,且製程為穩定狀態的假設下,找出製作時程與成品交期績效指標之最佳估計式,進而建立一套製作時程與成品交期績效指標之檢定程序,做為廠商監控內部各生產步驟之製作時程績效及成品交期績效管制之依據,亦可做為公司評估供應商是否能如期交貨之參考。
Process/product qualities (including reliability, lifetime, conforming rate etc.) and delivery time have received increasing attention in the highly competitive electronic industry. Various methods have been developed for assessing process/product quality performance. Process capability indices (PCIs) are used as a means to measure process performance. However, methods for assessing the performance of time-based quality characteristics (including lifetime, processing time and delivery time) of products have seldom been discussed. Two objectives relating to lifetime and delivery time of products are discussed in this study. The first objective is to utilize the PCIs to assess the lifetime performance of electronic components. The best estimator of lifetime performance index under an exponential process distribution is derived. The estimator is then utilized to construct the lower confidence limit for the true lifetime performance of electronic components. The lower confidence limit can be employed by the purchasers to determine whether the lifetime of the electronic components adheres to the required level. Manufacturers can utilize the proposed procedure to enhance process capability. The second objective is to develop effective performance indices to assess the performance of Processing time (PT) and Delivery time (DT) for very large scale integrated circuits (VLSI). The best estimators of the proposed performance indices are derived under the assumption of a normal process distribution. The PT and DT estimators are then used to construct the one-to-one relationship between the performance indices and conforming rate of DT or non-conforming rate of PT. Finally, the hypothesis testing procedures of the proposed PCIs are also developed. The testing procedure can be used to effectively assess whether DT or PT performance can satisfy customer's requirements.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT910031005
http://hdl.handle.net/11536/69761
顯示於類別:畢業論文