標題: 相位鎖定與延遲鎖定迴路於低成本測試機上之應用與研究
The Study of PLL and DLL and Its Application to Low Cost Tester
作者: 陳玉郎
Yu-Lang Chen
李 鎮 宜
Chen-Ye Lee
電機學院電子與光電學程
關鍵字: 鎖相迴路;PLL DLL
公開日期: 2001
摘要: 測試機上之Timing Generation(TG)是測試機台上時序的控制核心,它是加速測試機台的關鍵技術。在此,我們有別於用傳統DAC、電容與比較器的方法,而改為目前較為先進的技術。利用鎖相迴路,做為4倍頻,再以一個相位延遲鎖定迴路,產生控制電壓,使倍頻鎖相迴路之輸出週期再被除4。目前我們在較低階、較少成本之技術,TSMC .6U CMOS技術模擬,可以得到 400MHZ的鎖相迴路輸出,它的週期2.5NS,被相位延遲鎖定迴路除4後為0.625NS。0.625NS為測試機最小解析度,它們足以應用於100MHZ的測試機台。以成本、對溫度的敏感性與時序調準而論,它的電路小而且有利用鎖相迴路控制時序調準,對溫度與電源的敏感性可降低。解析度較差但是準確性(accuracy)並不遜於以前之設計, RMS accuracy <3PS
A timing generator (TG) is the most important part on the tester timing control system. It is the key factor for speeding up tester's cycle rate. Here, This research uses an alternative way to build our tester timing generator. It is different from the traditional methodology, and they used to build timing generator by current steering DAC, capacitor and comparator. In this thesis, it uses a phase locked loop to multiply the input clock rate by 4, and then use a delay locked loop to divide the clock period into 4 equal sections again. The PLL and DLL simulation have been accomplished by using lower level and lower cost technology, TSMC .6U CMOS technology. Its performance could have PLL output 400MHZ clock, and the DLL output minimum stable phase delay reach 0.625ns. 0.625ns is the minimum resolution to a tester's timing generator. We could use this circuit to supply 100MHZ data rate on a tester's TG. This methodology uses extern clock to adjust PLL and DLL output. They both used the feedback loop to control their output. So the immunity to the deviation of power supply and temperature is better than the traditional design. Although its resolution is larger, its' accuracy is still better, typical RMS accuracy < 3ps.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT901706043
http://hdl.handle.net/11536/69677
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