標題: 半導體後段製程誘發之高阻抗研究
Study of BEOL Process Induced High Resistance in IC's Manufacturing
作者: 林政綱
張國明
電機學院電子與光電學程
關鍵字: 製程誘發;後段製程;高阻抗;Process Induced Effects;BEOL
公開日期: 2001
摘要: 摘 要 這篇論文研究兩個關於半導體後段製程的主題。其一為製程誘發的高接觸窗阻抗,另一為製程誘發的金屬內連線異常片電阻。 在第一個主題中,發現接觸窗電阻在相同的製程條件下,不僅和接觸面積有關,而且與argon之濺擊蝕刻、接觸洞形狀及下緣金屬表面之抗反射層狀態有關。 在argon濺擊蝕刻時,加速的argon離子會濺擊接觸洞的內壁,導致內壁的氧化層剝落,而掉落至接觸洞的底部。這剝落的氧化層會縮小接觸窗的面積,影響接觸介面品質,而增加了接觸阻抗。 接觸洞的傾斜角也會影響接觸阻抗。傾斜角愈大,接觸洞內壁對於argon離子的接受面積也會增大。因此,剝落氧化層效應也會增加,而影響了接觸阻抗。 底層金屬的抗反射層之表面狀態也是重要的因素。在接觸洞蝕刻的過程中,遭受損傷的抗反射層將會導致高接觸阻抗。可得結論為:argon濺擊蝕刻後,鈦氧化物的部分殘留為導致高阻抗之主要因素。 在接觸窗蝕刻中產生的含鈦聚合物也是影響接觸阻抗的重要因素。在接觸窗蝕刻的配方中,被證實加入氮氣將可改善鈦聚合物的問題。採取鈦軟化蝕刻製程也可有效地去除鈦聚合物。 根據研究的結果顯示:較直的接觸洞形狀、恰當的argon濺擊條件、未受損傷的接觸介面及無聚合物的接觸洞可以得到較穩定的接觸阻抗。 本篇論文之另一研究主題為製程誘發的金屬內連線異常片電阻。顯影液氧化金屬內連線所產生的圓形缺陷會導致高片電阻及內連線的短路。實驗結果發現:採用較厚的抗反射層,內連線金屬表面臭氧處理及加入鈦應力紓解層皆能改善此圓形缺陷。 在光阻重工製程所導致的金屬殘留,也會影響內連線片電阻。內連線抗反射層之鈦氧化物會成為內連線蝕刻時的硬罩幕,此硬罩幕會變成蝕刻的障礙,而導致不完全蝕刻,造成金屬殘留。藉由控制光阻重工時的製程溫度,及使用液體去除液皆可有效地防止金屬殘留。不過上述之方法將會導致產能的降低與成本的提高。
Abstract In this thesis, there are two topics of BEOL (Back End of Layers) process to be studied. One is the study of process-induced high via contact resistance problem. The other is the study of process-induced abnormal interconnection line sheet resistance. On the first topic about the via hole contact resistance, it was interesting to find that the via hole contact resistance was not simply related to the contact area on the base of the same process conditions. It was found that all the Ar (argon) sputtering etch (before plug deposition), the via hole profile (taper angle) and the damaged TiN ARC (anti-reflective coating) layer of the bottom metal line would affect the via hole contact resistance. During argon sputtering process, the accelerated argon ions will sputter the sidewall of the via holes to cause chipping oxide drop on the bottom of the via hole. The chipping sidewall oxide will shrink the contact area, and impact the contact interface quality and finally increase the contact resistance. The taper angle of the via hole profile also affects the contact resistance. The more taper the via profile is, the larger the acceptance area of via sidewall is. Therefore, the chipping oxide effect increases and influences the contact resistance. The surface condition of the ARC layer of the bottom metal line is also an important factor. The damaged ARC layer surface during via etching will cause extremely high contact resistance. It was concluded that the incomplete titanium-oxide removal by argon sputtering is the dominant factor. Titanium contained polymers generated during via etching are also a key factor which impacts the via resistance. It was proved that nitrogen gas added in the via etching process would improve the Ti-polymer problem. It is also effective to adopt a Ti softened etching process to remove Ti polymers. According to the results of the study, to obtain a stable contact resistance is to get a more vertical via profile, an optimized argon sputtering condition, a non-damaged contact surface, and polymers free via holes. The other topic in this thesis is the study of process induced abnormal sheet resistance of interconnection lines. Circular defects resulting from the attack of the developer will cause high sheet resistance and short circuit of the interconnection lines. It is found that to get thicker ARC TiN, to adopt ozone treatment after metal film deposition, and to insert a stress relief layer of Ti all would improve the circular defects problem. Metal residues resulting from the rework process of photo resist also impact sheet resistance of the interconnection lines. The oxidation of the ARC titanium may be served as the hard mask during etching the line pattern. This hard mask is an etching obstacle which causes incomplete etching and results in metal residues. It was proved effectively to eliminate metal residues by controlling ashing temperature and with wet stripper. The disadvantages of these strategies are impacts on throughput and lots of cost.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT901706022
http://hdl.handle.net/11536/69653
顯示於類別:畢業論文