High-Reliability and Low-Capacitance Bond Pad Design for CMOS Integrated Circuits
|關鍵字:||銲墊;銲線固著度;拉線測試;推球測試;佈局;低電容銲墊;漏電流;熱衝擊試驗;bond pad;bond wire reliability;wire pull test;ball shear test;layout;low capacitance pad;leakage current;thermal shock test|
Wire bond package is still the mainstream of IC packages although different advanced package technologies, such as chip on board (COB), flip chip, chip scale package (CSP), and multi-chip module (MCM), are available today. In this thesis, there are three correlated approaches of bond pad designs of wire bond IC products proposed for reliability improvement, parasitic capacitance reduction, and layout area saving for system-on-a-chip (SOC) applications. During manufacture of wire bonding in packaged IC products, the breaking of bond wires and the peeling of bond pads occur frequently, which results open-circuit failure in IC products. There were several prior methods reported to overcome these problems by using additional process flows or special materials but all with additional cost. In this thesis, a layout method is proposed to improve the bond wire reliability in general CMOS processes. By changing the layout patterns of bond pads, the reliability of bond wires on bond pads can be improved. The proposed layout method for bond pad design is fully process-compatible to general CMOS processes. Large parasitic capacitance of conventional bond pad structure is a serious problem in high frequency IC application. A new structure design of bond pad is proposed to reduce its parasitic capacitance in general CMOS processes without extra process modification. The proposed bond pad, which is modified from the layout method for improving bond wire reliability, is constructed by connecting multi-layer metals and inserting additional diffusion layers into the substrate below the metal layers. The experimental results show that the proposed low-capacitance bond pad has a capacitance less than 50% of that in the traditional bond pad. The proposed bond pads can also keep the same good bonding reliability as that of traditional bond pad. To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices, which are designed under bond pads with different layout pattern designs of metal layers, was fabricated for verification. Threshold voltage, off-state drain current, and gate leakage current of these devices under bond pads were measured. After assembled in the wire bond package, the measurement results show that there are only little variations between devices under bond pads and devices beside bond pads. This discovery can be applied on saving layout area for on-chip ESD protection devices or I/O devices of IC products, especially when the IC’s have high pin counts.