標題: An efficient VLSI architecture for full-search block matching algorithms
作者: Lee, CY
Lu, MC
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-三月-1997
摘要: This paper presents a novel memory-based VLSI architecture for full search block matching algorithms. We propose a semi-systolic array to meet the requirements of high computational complexity, where data communications are handled in two styles: (I) global connections for search data and (2) local connections for partial sum. Data flow is handled by a multiple-port memory bank so that all processor elements function on target data items. Thus hardware efficiency achieved can be up to 100%. Both semi-systolic array structure and related memory management strategies for full-search block matching algorithms are highlighted and discussed in detail in the paper.
URI: http://hdl.handle.net/11536/696
ISSN: 0922-5773
期刊: JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
Volume: 15
Issue: 3
起始頁: 275
結束頁: 282
顯示於類別:期刊論文


文件中的檔案:

  1. A1997XE96800006.pdf