Title: 倒傳遞類神經網路之VLSI設計
VLSI Design of Back Propagation Networks with On-Chip Learning
Authors: 郭功耀
Gang-Yaw Kuo
Jyh-Yeong Chang
Lan-Rong Dung
Keywords: 類神經網路;超大型積體電路;Neural Networks;VLSI
Issue Date: 2001
Abstract: 為了使類神經網路擁有特定的能力,必須反覆學習直到每個輸入都能正確對應到所需要的輸出為止,當需要學習的資料很龐大時,學習的過程往往需要很長的一段時間。因此,許多增快學習的方法便被廣泛的討論與研究。我們若以超大型積體電路去實現類神經網路,並且使其能夠與複雜的計算機系統溝通配合,便可有效的縮短學習所消耗的時間。 在本論文中,我們利用超大型積體電路來實現倒傳遞類神經網路,這個晶片整合了學習部份以及回想部份,並且使得網路的輸入層、隱藏層以及輸出層的神經元個數能夠隨需求而任意調整。整個架構是基於單一指令多資料的精神,我們利用有限個數的運算單元去執行所需的運算,這些運算單元可由控制單元自由調度,而不僅限於某個特定的任務,最後我們以蝴蝶花分類問題以及點矩陣英文字母辨識來驗證我們的設計。
Nowadays, the industry of information appliances and communication products is growing rapidly. Intelligent products will become the key feature in the future. Artificial neural networks have the capabilities to learn and recall and are highly parallel. However, conventional computers do not support parallel computing and learning capability that are inherent in neural networks. Among the existing parallel architectures, SIMD (Single Instruction stream Multiple Data) is the most suitable for the implementation of BPN (back propagation networks). Therefore, the proposed architecture is based on SIMD. The proposed architecture uses limited number of PEs to fulfill all the operations needed for the recalling phase and the learning phase. The aim of the proposed architecture is not intended for one specific application. Therefore, the proposed BPN chip can be reconfigured to any BPN structure by modifying some parameters. Finally, two real cases are used to verify our design.
Appears in Collections:Thesis