Title: 1.8GHz DCS-1800金氧半射頻頻率合成器的設計
The Design of A 1.8GHz CMOS RF Frequency Synthesizer for DCS-1800 Application
Authors: 許民傑
Yao-Huang Kao
Keywords: 金氧半;DCS-1800;壓控振盪器;正單相時脈電路;電感;相位雜訊;分數式;頻率合成器;CMOS;DCS-1800;VCO;TSPC;inductor;phase noise;fractional-N;frequency synthesizer
Issue Date: 2001
Abstract: 本論文中實現一個具有頻率的準確度和解析度的內含單晶LC金氧半壓控振盪器的射頻頻率合成器。金氧半壓控振盪器的架構為互補式雙交叉耦合對(complementary cross-coupled pair),並使用積體式電感電容共振調諧電路,將電感的線寬最佳化,以提升品質因素﹝Quality Factor﹞。另外提出一個設計低雜訊壓控振盪器的流程,以及一個準確預估相位雜訊的方法。對於預除器的設計,採用正單相時脈電路的D型正反器並結合邏輯閘,以減小延遲達到快速的目的。最後提出一個0.35μm符合DCS-1800規格的分數式射頻頻率合成器,可以涵蓋發射頻率和接收頻率1.728GHz~1.824GHz和1.782GHz~1.881GHz,相位雜訊在600KHz和3MHz分別是-120.1dBc/Hz以及-134.3dBc/Hz。
Phase-locked loop (PLL) based fractional-N frequency synthesizers have played an important role in RF front-ends. The purpose of this work is to implement a RF frequency synthesizer with a monolithic LC-tank voltage-controlled oscillator (VCO). The architecture of VCO is complementary cross-coupled pairs. The Quality factor of the on-chip spiral inductor is optimized by varying the metal width in each turn. A procedure of designing a low phase noise oscillator is provided. And the prediction of phase noise is also indicated. High-speed dual-modulus prescaler is implemented by merging the so-called True Single-Phase Clock (TSPC) D flip-flops (DFFs) as well as logic gates to reduce propagation delay. Finally, the fractional-N frequency synthesizer for DCS-1800 application is implemented in 0.35μm CMOS technology. The synthesized frequency is 1.728GHz to 1.824GHz and 1.782GHz to 1.881GHz for TX and RX, respectively. The phase noise is -120.1dBc/Hz @600KHz and -134.3dBc/Hz @3MHz.
Appears in Collections:Thesis