The Investigation of Gate Oxide Interface and Process-Induced Device Reliability in Deep-Submicron and Nanometer CMOS Devices
Steve S. Chung
|關鍵字:||電荷幫浦法;熱載子可靠性問題;半導體界面缺陷;汲極結構;淺溝狀隔離法;電漿蝕刻傷害;超薄/穿隧氧化層;有效通道長度;charge pumping (CP) technique;hot carrier reliability;semiconductor interface trap;drain structure;shallow-trench-isolation;plasma induced damage;ultra-thin/direct tunneling regime gate oxide;effective channel length|
The charge pumping (CP) technique has been widely used for the characterization of hot carrier (HC) reliability and the evaluation of semiconductor interface. The objective of this dissertation is to employ this CP technique for investigating the hot carrier induced and process-induced device reliabilities for device dimensions from deep-submicron to nanometer scale. In addition, a more sophisticated CP technique will be developed for the characterization of nanometer CMOS devices. First of all, since submicron (with LDD) and deep-submicron (with S/D extension) nMOSFET’s have different drain structures, it exhibits different mechanisms of drain current degradation. There exists an ambiguity that drain current degradation depends not only on gate oxide thickness but also on device drain structure. No definite method can provide an adequate solution for these two generations of devices. In this work, a new criterion for HC reliability evaluation has been proposed as a good monitor for the drain current degradation. This monitor uses total values of interface traps generated inside effective channel length, instead of the commonly used substrate current (IB), impact ionization rate (ID/IB), or peak/average values of interface traps. The approach has been successfully demonstrated to be valid for two generations of submicron (with LDD structure) and deep-submicron (with S/D extension structure) nMOSFET’s. On the other hand, the shallow-trench-isolation (STI) has become the main isolation technique to replace the local oxidation of Si (LOCOS) isolation. While, the STI CMOS devices exhibit severe degradation after hot-carrier stress with a reducing channel width. In this work, new degradation models and mechanisms has been developed to explain the width dependent degradation, in which the effective interface trap generation for nMOSFET’s and channel-shortening length for pMOSFET’s have been used as good monitors. Both HC effects in n- and pMOSFET’s are found to be strongly related to the mechanical stress on the border of the trench. Furthermore, plasma interaction with the silicon (Si) wafer during the plasma etching process of MOSFET has been known to produce serious damage, which affects the oxide quality, device reliability and wafer uniformity. There are two types of damage induced by plasma etching process- plasma-charging damage generated in the gate oxide and channel region, and plasma edge damage generated near the gate edge. This study will provide a CP profiling technique to evaluate the enhanced HC effect by the plasma-charging. In the mean time, a new three-phase plasma damage mechanism has also been proposed to clarify the enhanced degradation for both n- and pMOSFET’s Finally, in the era of sub-100nm manufacturing technique, it has reached the fundamental limits for device scaling, such as direct tunneling leakage and quantum effect. This makes the analysis of electrical characteristics in a nano-scaled device more difficult, especially the monitor of oxide quality and the evaluation of device reliability. In this study, we have also developed a new low leakage CP technique for interface trap characterization of very-short dimension and ultra-thin gate oxide devices. Even for a gate oxide thickness down to the 1nm range, this CP technique will still be valid. Moreover, this technique can also be used to calculate the effective channel length in a sub-100nm device, which is the smallest dimension of the length extraction method up-to-date. In short, this dissertation has successfully employed the CP technique to investigate the hot carrier induced and process-induced device reliabilities. Device mechanism and physical model have been well developed for the studies of the HC effect, the STI induced mechanism stress, and the plasma damage enhanced degradation. Again, a new low leakage CP method has been provided for the sub-100nm device with gate oxide in the range of direct tunneling regime. This newly developed CP technique is believed to be a very powerful tool for the characterization of next generation nanometer CMOS devices.
|Appears in Collections:||Thesis|