標題: 第三代寬頻分碼多工存取系統基頻接收機之數位信號處理及積體電路設計
DSP Realization and ASIC Design of 3G WCDMA Baseband Receiver
作者: 羅友成
You-Cheng Luo
陳紹基
Sau-Gee Chen
電子研究所
關鍵字: 寬頻分碼多工存取;基頻接收機;耙狀接收機;通道估測;WCDMA;baseband receiver;Rake receiver;channel estimation
公開日期: 2001
摘要: 本論文主要提出第三代行動通訊(寬頻分碼多工存取)系統中基頻接收機之數位訊號處理器的實現及積體電路架構的設計。在一個寬頻分碼多工存取系統中,基頻接收機主要包含碼同步電路、通道估測器及耙狀接收機。首先,我們針對耙狀接收機、線性內插通道估測與滑動窗型通道估測、碼同步中信號路徑追蹤及搜尋,利用C語言做一個完整的系統模擬。接著,利用Innovative Integration公司的Quatro6x DSP板實現此一基頻接收器,並達到即時(real-time)運算處理。最後,並於論文中提出一個適合以積體電路實現的基頻接收機架構,結合低功率相關器的設計與低複雜度之相關運算演算法分析設計,以達到低功率消耗及高效能設計的基頻接收機。
In this thesis, DSP realization and ASIC architecture design of the baseband receiver of the third Generation Mobile Communication (Wideband Code Division Multiple Access) systems were presented. In WCDMA system, a baseband receiver includes Rake receiver, channel estimator, and code synchronization circuit. First, we simulated and analyzed the whole baseband receiver system in C language for Rake receiver, channel estimation of linear interpolation and sliding window method, and path search and tracking in code synchronization. We implement the WCDMA baseband receiver on Innovative Integration Company’s Quatro6x DSP board. Finally, the WCDMA baseband receiver architecture suitable for ASIC design is proposed. With low-power correlator design and low-complexity correlation algorithms design, the architecture can achieve a low-power consumption and high performance baseband receiver.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT900428120
http://hdl.handle.net/11536/68810
Appears in Collections:Thesis