標題: Enhanced Hole Gate Direct Tunneling Current in Process-Induced Uniaxial Compressive Stress p-MOSFETs
作者: Hsu, Chih-Yu
Lee, Chien-Chih
Lin, Yi-Tang
Hsieh, Chen-Yu
Chen, Ming-Jer
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Layout;mechanical stress;MOSFET;piezoresistance;shallow trench isolation (STI);tunneling
公開日期: 1-Aug-2009
摘要: On a nominally 1.27-nm-thick gate oxide p-MOSFET with shallow trench isolation (STI) longitudinal compressive mechanical stress, hole gate direct tunneling current in inversion is measured across the wafer. The resulting average gate current exhibits an increasing trend with STI compressive stress. However, this is exactly contrary to the currently recognized trend: hole gate direct tunneling current decreases with externally applied compressive stress, which is due to the strain-altered valence-band splitting. To determine the mechanisms responsible, a quantum strain simulator is established, and its validity is confirmed. The simulator then systematically leads us to the finding of the origin: a reduction in the physical gate oxide thickness, with the accuracy identified down to 0.001 nm, occurs under the influence of the STI compressive stress. The strain-retarded oxide growth rate can significantly enhance hole direct tunneling and thereby reverse the conventional trend due to the strain-altered valence-band splitting.
URI: http://dx.doi.org/10.1109/TED.2009.2024024
http://hdl.handle.net/11536/6848
ISSN: 0018-9383
DOI: 10.1109/TED.2009.2024024
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 56
Issue: 8
起始頁: 1667
結束頁: 1673
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