標題: Random-Dopant-Induced Variability in Nano-CMOS Devices and Digital Circuits
作者: Li, Yiming
Hwang, Chih-Hong
Li, Tien-Yeh
電信工程研究所
Institute of Communications Engineering
關鍵字: Characteristic fluctuation;modeling and simulation;nanoscale digital IC;random-dopant effect;timing
公開日期: 1-八月-2009
摘要: The impact of the number and position of discrete dopants on device characteristics is crucial in determining the transient behavior of nanoscale circuits. An experimentally validated coupled device-circuit simulation was conducted to investigate the discrete-dopant-induced timing-characteristic fluctuations in 16-nm-gate CMOS circuits. The random-doping effect may induce 18.9% gate-capacitance fluctuation, affecting the intrinsic device gate delay and circuit timing. For a 16-nm-gate CMOS inverter, 0.036-, 0.021-, 0.105-, and 0.108-ps fluctuations in rise time, fall time, low-to-high delay time, and high-to-low delay time are found. The timing fluctuations of NAND and NOR circuits are increased, as the number of transistors increased. Because of the same number of transistors in circuits, the timing fluctuation of NAND and NOR are expected to be similar. However, due to the different function and device operation status of circuit, the timing fluctuation is quite different. The function-and circuit-topology-dependent characteristic fluctuations caused by random nature of discrete dopants are found. This paper provides an insight into random-dopant-induced intrinsic timing fluctuations, which can, in turn, be used to optimize nanoscale CMOS field-effect-transistor circuits.
URI: http://dx.doi.org/10.1109/TED.2009.2022692
http://hdl.handle.net/11536/6845
ISSN: 0018-9383
DOI: 10.1109/TED.2009.2022692
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 56
Issue: 8
起始頁: 1588
結束頁: 1597
顯示於類別:期刊論文


文件中的檔案:

  1. 000268282400005.pdf