The Development of Flip-Chip Package Technology for High Frequency GaAs Device Applications
Shin Chen Huang
Edward Y. Chang
論文中並對砷化鎵低雜訊電晶體之覆晶構裝製程對元件電性影響加以討論。覆晶構裝前後之高頻特性量測結果顯示本實驗應用低介電材料Benzocyclobutene (BCB)作為構裝的絕緣層能有效地抑制閘極-汲極間的回饋電容；此外，在18 GHz 的操作頻率下，構裝後之雜訊指數上升了0.54 dB，而增益則是略降了1.2 dB；本研究中並由S參數導出低雜訊電晶體小訊號等效電路，此模型之建立有助於改善元件構裝後的高頻特性表現。
This thesis presents a low cost solder bumping flip chip packaging technology for high frequency GaAs device applications to replace the wire bonding technology to achieve better RF performance for the devices at high frequencies. The developed process combines the copper-metallized UBM and electroplated eutectic solder bump on a GaAs PHEMT (Pseudomorphic High Electron Mobility Transistor) with an electroless plated Ni/Cu post on AlN substrate. The GaAs PHEMT die is flip-chip mounted. The flip- chip assembly process is well documented which is a stable and reproducible packaging process. DC and RF characteristics of the GaAs PHEMT before and after packaging process were investigated. The RF measurement before and after flip chip assembly reveals that low k material Benzocyclobutene (BCB) serving as the wafer passivation dielectric efficiently constrains the gate-drain feedback capacitance. In addition, at the operation frequency of 18 GHz, the gain of the flip chip packaged PHEMT drops about 1.2 dB lower and the noise figure is about 0.54 dB higher than before packaging. A small signal equivalent circuit model was made by fitting the measured s-parameters. The establishment of the device model will be helpful for improving the RF performance of the packaged device. In conclusion, the fabrication process for flip chip packaging of high frequency GaAs device is developed. The influences of the packaging process on the electrical performance of the device were discussed as well. The results of this study would serve as the foundation for future study of the flip chip packaging technology for high frequency devices.
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