Dispatching rules based on unexpected waiting time of eafer lots
Liu Chi Chang
Dr. Muh-Cherng Wu
|關鍵字:||派工法則;異常等待;生產週期時間;dispatching rules;unexpected waiting time;committed cycle time|
This research develops several dispatching rules for IC foundries in order to improve the on-time delivery. On-time delivery is a key performance indicator in an IC foundry. Yet, it cannot be well controlled due to the occurrence of unexpected events such as machine down. This research decomposes the cycle time into three parts: processing time, expected waiting time, and unexpected waiting time. The expected waiting time concerns the waiting of lots in the case of no unexpected events. The unexpected waiting is concerned with the waiting of lots caused by unexpected events. In this research, each lot is given a time buffer to accommodate the unexpected events. The basic idea is that lots with less remaining time buffer is more urgent and has higher dispatching priority. Several dispatching indicators based on this idea has been developed and tested by simulation. Simulation results using 10 seeds show that one of the proposed dispatching rules, MCR (modified Critical Ratio), in average is better than other dispatching methods in literature.