標題: 低耗能並考慮低成本效益之系統晶片測試策略
Low Power and Low Test Data Volume Testing for Scan Design VLSI
作者: 林世平
Shih Ping Lin
Chung-Len Lee
關鍵字: 測試;低功率測試;測試資料壓縮;testing;low power testing;test data compression
公開日期: 2007
摘要: 本論文就關於當前測試所面臨之問題:龐大之測試資料量以及過高的測試能量,做ㄧ完整的研究探討。針對此兩個測試問題,我們提出幾個解決方案。首先,提出一個類似矩陣架構之掃描方式,並搭配一個新設計之掃描暫存器,來構成掃描矩陣。此架構藉由略過不必要的掃描暫存器,減少掃描暫存器與電路內部的變化次數,來降低測試向量輸入時造成的能量消耗。我們提出之掃描暫存器不會降低待測物的運作效能,同時能降低時脈樹之能量消耗。由實驗結果顯示此架構可大幅降低測試時產生的能量消耗。 其次,我們提出一個基於隨機存取掃描之混合式測試流程。藉由觀察傳統的測試向量壓縮方法之不足處,我們提出幾個改進的技巧,並搭配混合式測試的流程來增進測試效率:(1)改進傳統靜態壓縮的方式,使壓縮後不會降增加位元翻轉次數;(2)檢視各種模組,用來預估含不確定位元之測試向量重新排列時造成之花費(位元翻轉),並找出最有效之模組;(3)提出向量捨去的方法,可以保證錯誤涵蓋率不會因捨去後而降低。實驗結果顯示此提出之流程可以很有效率地減少位元翻轉次數,平均來說可以達到百分之八十六之壓縮率與增加近十倍的效能。 之後我們提出ㄧ個適用於測試系統晶片之測試資料壓縮方法,採用一個能支援各種區塊大小之適應性編碼方法,同時利用勘入之記憶體與一個解碼器來做測試資料解壓縮。此方式避免了傳統會因選擇之區塊大小而影響壓縮率之問題,我們同時提出ㄧ個能降低測試能量之技巧,來取捨壓縮率與測試能量之平衡,我們也採用兩階段之混合式測試來比較測試效能之增進。實驗結果證明此方式能有效降低測試資料量與測試能量,並且隨著測試電路之複雜度增加,整體效能亦能提升。 最後,我們提出一個針對具多重掃描鏈之待測物之低功率測試資料壓縮方法,稱為多階層次資料複製。此方法利用測試項量中之不確定位元來做不同層次的複製,以達到資料壓縮,我們並系統化分析此方式可以達到之壓縮率以及降低之能量。多層次資料複製不但可以直接針對測試向量做壓縮,亦可整合至測試向量產生器中提升效能。我們在實驗中也做了詳盡的比較,證明提出之多層次資料複製具有高壓縮率與低功率之特性,同時所付出之面積成本亦非常少,我們也與習知技術比較,列出此多階層次資料複製之各項優點。
Scan design is now a necessary practice for today’s ICs when considering their testing. As the size of today’s ICs now becomes tremendously large, the traditional scan test becomes inefficient and troublesome due to two problems: the large test data volume which leads to unaffordable test application time and the high test power which may cause reliability problem to ICs. This dissertation makes a comprehensive study on these two test challenges. We propose several solutions. First, we proposes a scan test architecture like matrix where a new scan cell is invented to be bypassed during pattern shifting when it is not addressed. This reduces the number of transitions of scan cells and the circuit under test (CUT) hence reduces the power consumption. In addition, the scan cell does not introduce any penalty on degrading the performance of the CUT. Moreover, we also adopt a design to reduce the power of clock tree. Experimental results show that it can achieve nearly 99% power savings for large size designs. Next, based on Random Access Scan (RAS), we propose a cocktail scan strategy. After surveying previous works, we present several improved strategies to improve the efficiency on test compression. These are: (1) a constrained static compaction, which is a compaction strategy to keep the number of bit flips the same after test cubes are compacted; (2) optimum reordering of test cubes: which is the best ordering of test cubes and is adopted by examining several cost models to estimate the number of bit flips; (3) test cube dropping: a method to drop test cubes while guarantee the same fault coverage. Experimental results show that the adoption of the above strategies is very effective in reducing the number of bit flips, leading to an 86% reduction in test data and ten times of speedup in test application time. Thirdly, we propose an encoding scheme, Adaptive Encoding, which is suitable for test data compression in System-on-Chip (SoC), by utilizing an embedded memory and encoder. The conventional test data encoding schemes usually suffer the drawback that the compression rate is affected by the block size, leading inefficiency in compressing test data. The proposed scheme supports variable block size encoding, thus eliminates the above drawback and improves the encoding efficiency. In addition, we also adopt a hybrid test technique to further reduce the volume of test data. We also try to make consideration of making tradeoff between the test compression rate and the test power during the above process. Experimental results show that the proposed method effectively reduces the volume of test data and test power. More specifically, we can reduce the test energy by 91.60% and reduce the peak power by 15.57% at the expense of 10.82% loss in test compression. Finally, we propose a Multilayer Data Copy (MDC) scheme, which is very suitable for designs with large number of scan chains, to obtain high test compression with low-power testing. This scheme proposes an architecture which performs two operations, Copy and Shift, to achieve high test compression rate by exploiting don’t care bits of test patterns. MDC can not only be used to compress test data sets but also be incorporated into automatic test pattern generator (ATPG) to give better efficiency. Similarly, we also consider test power reduction when do test data compression. Systematic study on this scheme shows that the schem has high compression rate and low testing power but has a negligible area overhead.
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