標題: 高性能低溫多晶矽薄膜電晶體之製程技術與特性研究
Study on the Process Technologies and Characteristics of High-Performance Low Temperature Polycrystalline Silicon Thin-Film Transistors
作者: 蔡春乾
Chun-Chien Tsai
鄭晃忠
Huang-Chung Cheng
電子研究所
關鍵字: 薄膜電晶體;低溫多晶矽;二極體倍頻固態連續波雷射;準分子雷射;雷射結晶法;Thin film transistors;Low temperature polycrystalline silicon;Diode-pumped solid-state continuous-wave laser;excimer laser;laser crystallization
公開日期: 2007
摘要: 多晶矽薄膜電晶體因為具有較高的載子移動率,及可將周邊驅動電路與液晶面板積體化至玻璃基板上來降低液晶顯示器之生產成本的優勢,使得它成為液晶顯示技術應用中的關鍵元件,並且在高附加價值與多功能整合的系統面板(System-on-Panel)的應用及三維積體電路(3-D ICs)的實現上具有很大的潛力。在現階段,採用準分子雷射退火法對非晶矽薄膜進行再結晶是最有潛力的量產結晶技術,藉由達到快速熔融與固化再結晶的方法,可得到一高品質的多晶矽薄膜並且可以保持玻璃基板不受到高溫的影響。雖然透過準分子雷射可有效的提升多晶矽層的結晶性,但此方法仍有些許缺點,如隨機的晶粒邊界及晶粒分佈、大晶粒的製程窗口較窄小、主動層和介電層之間造成大的粗糙界面等等。在本篇論文裡,我們將提出多項雷射結晶方法及元件結構來增進低溫多晶矽薄膜電晶體的特性。 首先,為了改善低溫多晶矽薄膜電晶體的電特性,我們先針對元件通道的多晶矽薄膜結晶性進行改善。一種我們具有晶粒邊界位置控制的底閘極低溫多晶矽薄膜電晶體方法將被提出而加以探討。其結晶機制敘述如下,因為底閘極結構邊緣台階區提供了較厚非晶矽層,在準分子雷射退火時,我們只需將雷射能量控制在可以使薄區的非晶矽薄膜完全熔解的能量密度以上,同時讓厚區的非晶矽薄膜部分熔解而確保留下部分微晶矽作為晶種,就可以得到一致分佈的大型晶粒成長,因此可以提升薄膜的均勻性及元件的效能。由實驗的結果分析可知,我們可以得到最大長度約為0.85μm長的人為控制晶粒。我們也製作出單一晶粒邊界的低溫多晶矽薄膜電晶體,其載子移動率可達到 330cm2 / V-s,同時閘極引起的汲極漏電和紐結效應也減少了,而且元件的均勻性也大幅提升。而且在閘極偏壓的可靠度量測之下,我們發現單一晶粒邊界的底閘極低溫多晶矽薄膜電晶體有較小的起始電壓漂移量及較高的崩潰電場,因此更適用於元件的微小化。 雖然單一晶粒邊界的底閘極低溫多晶矽薄膜電晶體表現出良好的電特性,由於偏離的黃光微影製程,造成源極(汲極)相對於閘極的離子佈植不對稱,使的元件的電特性不對稱。因此我們結合背後曝光方法與單一晶粒邊界的底閘極低溫多晶矽薄膜電晶體製作出新穎之自我對準的單一晶粒邊界的底閘極低溫多晶矽薄膜電晶體。我們不僅包留了單一晶粒邊界的底閘極低溫多晶矽薄膜電晶體的良好特性,自我對準的單一晶粒邊界的底閘極低溫多晶矽薄膜電晶體也表現出良好的電對稱性。如此一來我們更能將自我對準的單一晶粒邊界的底閘極低溫多晶矽薄膜電晶體應用於畫素電路中的開關元件。 將元件縮小,雖然可以進一步的提升多晶矽薄膜電晶體的電特性,但是也遭遇到嚴重的短通道效應,尤其是薄膜電晶體因為本身通道較多的缺陷及低溫製程,短通道效應更是較傳統金氧半場效電晶體明顯嚴重,因此雙閘極結構結合通道晶粒成長的技術也在本論文提出,藉由該底閘極的準分子雷射結晶法,通道中的晶粒成長控制來得到較好的結晶性,與上下雙閘極對通道的耦合來改善閘極對通道的控制能力,其N型元件以單通道長度換算之等效載子移動率可超過 1050 cm2/V-s,而P型元件則超過 480 cm2/V-s。此元件有高驅動電流,高開關電流比,優異的短通道抵抗力,較陡峭之次臨界擺幅,較小的汲極誘導能障下降(DIBL),同時均勻性也得到改善。 雖然利用底閘極的準分子雷射結晶技術可以有效的改善多晶矽薄膜結晶性,但是不可避免的,在低溫多晶矽薄膜電晶體的通道中存在一高角度的晶粒邊界,進而對於元件電特性造成劣化及耐用度上的問題。因此我們提出了一個新穎的側向雷射結晶方式-間隙壁式結晶法-來消彌通道中的高角度的晶粒邊界,其結晶機制是利用空間上的熱傳機制來達成晶粒橫向成長的目的,首先利用傳統間隙壁法製作出50奈米大小的晶種,並在局部微小區域產生兩種厚度不同的非晶矽薄膜,當準分子雷射照射在此一結構上,使較薄的區域完全熔融時,而間隙壁較厚的區域部分熔解,晶粒便會以這些非晶矽間隙壁為結晶起始點,做橫向成長,再藉由適當的安排間隙壁與元件通道的相關位置,我們將可以消除通道中所有垂直電流方向的晶粒邊界,更進一步的改善元件的載子移動率與均勻性。以通道長度為2μm的元件為例,以此結晶方法做出的低溫多晶矽薄膜電晶體其載子移動率可以到達288 cm2/V-s,而傳統的元件的載子移動率只有129 cm2/V-s.。 為了更進一步的提升多晶矽薄膜電晶體的驅動能力,達到一類似絕緣層上覆晶矽(Silicon-On-Insulator-like)金氧半場效電晶體的效能,進而實現SOP或3D ICs的夢想,無晶粒邊界的單晶矽電晶體(Single-grain TFT)是最終目標的元件,因此我們提出了一個新穎的二維晶粒控制側向成長的雷射結晶方式,結合上述之非晶矽間隙壁及先定義矽薄膜之結晶法來分別達成X軸及Y軸的熱梯度,進而完成單晶粒之側向晶粒成長。從實驗分析結果發現,我們可以得到一直徑為1.8μm大的圓型週期性單晶粒矽薄膜。以通道長度為1.5μm的元件為例,以此結晶方法做出的低溫多晶矽薄膜電晶體其載子移動率可以到達308 cm2/V-s,開關電流比則高於10的8次方,且具高度的均勻性。 上述的結晶法雖然可以達成大晶粒成長及高性能薄膜電晶體的目的,而本論文亦提出一新式的固態連續波雷射(Continuous-wave Laser)退火技術,直接利用控制掃瞄速度及掃瞄功率來達成晶粒橫向成長。一長度達15μm的多晶矽薄膜晶粒可以製作出來而不損傷到玻璃基板,而實驗結果亦顯示矽薄膜具有極佳的結晶性,同時其晶粒邊界位置的表面粗糙度極為平順。利用連續波雷射結晶法製作的低溫多晶矽薄膜電晶體擁有優異的電特性,例如較高的電子移動率(n通道的其載子移動率可達500cm2/V-s,而p通道的為200cm2/V-s)及較高的開關電流比。另外,我們也探討了利用連續波雷射在摻雜活化的退火特性,其由四點探針分析可得一片電阻低於 50 Ω/□,同時由二次離子質譜分析儀得到一均勻分佈的摻雜雜質,因此連續波雷射退火法是一個低熱預算和高效率的活化方法。由於連續波雷射結晶法製作大晶粒流程十分簡單,因此使用連續波結晶法製作的低溫多晶矽薄膜電晶體的亦極適合於未來系統面板的應用。
Low-temperature polycrystalline silicon (LTPS)thin film transistors (TFTs) have been extensively studied for active matrix flat panel displays (AMFPDs), full-function system-on-panel (SOP), and potential for the 3-dimensional integrated circuits (3D-ICs) applications owing to their high field-effect mobility, low power consumption¬¬, high reliability, high resolution, and low fabrication cost by the integration of driver and controller ICs. At this moment, excimer laser crystallization (ELC) of amorphous silicon (a-Si) thin films seems to be the most promising method for its great advantages in mass production and high quality silicon grains without damage to the glass/plastic substrates. Although large grains can be attained in the super lateral growth (SLG) regime by ELC, many fine grains still spread between these large grains due to the narrow process window for producing large-grain poly-Si and highly rough interface. Consequently, non-uniform and randomly distributed poly-Si grains will result in the large variation of TFT performance when the laser energy density is controlled in the SLG regime, especially for the small-dimensional TFTs. In this thesis, many approaches, including techniques of excimer-laser-crystallized poly-Si thin films, advanced device structures, and diode-pumped solid-state (DPSS) continuous-wave (CW) laser annealing, have been proposed to further enhance the performance of LTPS TFTs. At first, from the perspective of improving channel material quality, LTPS TFTs with bottom gates (BG) have been demonstrated to achieve large silicon grains due to the lateral grain growth. In this method, a-Si thin film with two kinds of thicknesses in a local region was formed by the deposition of a-Si films on the plateau structure. When the excimer laser irradiation is applied on the a-Si thin film, the applied laser energy density is controlled to completely melt the thin region of a-Si film in the channel region but partially melted the thick region of a-Si film near the edges of bottom gate. Therefore, a lateral temperature gradient can be produced between the local thin and thick regions of a-Si film, and the lateral grain growth started from the un-melted silicon solid seed at the base neighbor to the bottom-gate corner, and extended toward the completely melted region until the solid-melt interface from opposite direction impinges. From material analyses, it can be observed that the large longitudinal grains artificially grown of about 0.85 μm in size were observed in the device channel region. Therefore, high-performance BG LTPS-TFTs have been demonstrated with the field-effect mobility exceeding 330cm2/V-s, low GIDL effect, suppressed kink current, and improved device uniformity due to the large silicon grains. Moreover, the BG TFTs reveal higher breakdown voltage and better reliability due to the smooth interface between gate dielectric and poly-Si channel films as thinner gate oxide were employed without additional processes or materials. The improved breakdown and driving characteristics imply that the proposed BG-TFT structure is more suitable for the device-scaled-down applications. Although BG LTPS-TFTs exhibit superior electrical characteristics, asymmetrical electrical characteristics are also observed due to the misaligned process effect. Therefore, a self–aligned (SA) bottom-gate TFT with appropriate channel length has been fabricated by the simple ELC and backside exposure. As a result, not only all the advantages of BG LTPS-TFTs with lateral silicon grains, but also the symmetrical electrical characteristics can be also observed in SA BG LTPS-TFTs. Consequently, SA-BG TFTs with the channel length of 1μm exhibited field-effect-mobility reaching 193 cm2/Vs without hydrogenation, while the mobility of the conventional non-SA-BG TFTs and conventional SA top-gate ones were about 17.8 cm2/Vs and 103 cm2/Vs, respectively. Shrinking the device size is an effective way to improving the device performance, but poor short-channel effects (SCE) is encountered owing to the insufficient gate controllability. Novel high-performance LTPS TFTs with double-gate (DG) structure and controlled lateral grain growth have been demonstrated by excimer laser crystallization. Because of the double gate operation mode and lateral silicon grains formed in the channel region, the devices have a higher driving current, steeper subthreshold slope, superior short-channel effect immunity, and suppression of the floating-body effect. The proposed DG TFTs (W/L = 1/1 μm) have the equivalent field-effect-mobility exceeding 1050 cm2/Vs for the N-channel device, 480 cm2/Vs for the P-channel device, on/off current ratio higher than 1E9, smaller DIBL, and excellent device uniformity. Although the crystallinity of poly-Si thin film can be effectively enhanced via ELC with bottom-gate structure, it is inevitable that there is a high angle grain boundary in the middle of channel region, which degrades the TFT performance and reliability. A novel laser crystallization method which can remove the high angle grain boundary and produce the large and uniform grains in the desired local region is proposed to improve the field-effect mobility as well as the device uniformity. Periodically lateral silicon grains with 2μm in length can be artificially grown in the channel regions via the amorphous silicon spacer structure with excimer laser irradiation. By the way, such periodically large and lateral grains in the TFTs would achieve high field-effect mobility of 298 cm2/Vs, as compared with the conventional ones of 128 cm2/Vs. In addition, the device-to-device uniformity could be improved due to this location-manipulated lateral silicon grains. In order to further improve the performance of LTPS TFTs, single-grain TFT in which the channel is grain-boundary-free will exhibit SOI-like performance to satisfy the requirements of system on panel. A new crystallization technology for producing two-dimensional lateral grain growth, aiming at single-grain TFT, has been developed by excimer laser irradiation relying on the spatially temperature distribution at the artificially sites. The high quality silicon grains are controlled via manipulating super lateral growth phenomenon by spatially two kinds of silicon films and pre-patterned structure. An array of 1.8-μm-sized disklike silicon grains is formed periodically. Not only high-performance poly-Si TFTs with field-effect-mobility reaching 308 cm2/Vs but also excellent device uniformity are demonstrated owing to the artificially-controlled lateral grain growth. Proposed poly-Si TFTs, therefore, have great potential for the future SOP and 3D-ICs applications. Although the aforementioned laser crystallization methods can fabricate large homogeneous silicon grains and high-performance LTPS TFTs, another crystallization approach, a new and simple DPSS CW laser crystallization, is also proposed to produce lateral grain growth via controlling the laser scanning speed and laser power. According to the experimental results, a directional river-like lateral Si grain growth with tens of micron, flat surface morphology, and excellent crystallinity are achieved without damage to the glass substrates. As a result, ultra-high performance CW laser-annealed LTPS-TFTs have been fabricated on the oxidized silicon wafer for the first time with field-effect mobility exceeding 504 cm2/V-s for n-channel devices and 220 cm2/V-s for p-channel devices. It is also found that CW laser annealing is a low-thermal-budget and high-efficiency dopant activation method attributed to the low sheet resistance and uniformly redistributed dopant profiles after CW laser annealing. Because of the simple process, continuous-wave laser-annealed LTPS TFTs are very promising for the future SOP, 3D-ICs, and solar cell applications.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009211814
http://hdl.handle.net/11536/67856
Appears in Collections:Thesis


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