Title: 使用有限資源排程之離散小波轉換處理器設計
Generic DWT Processors using Limited Resource Scheduling
Authors: 魏廷勳
Lan-Rong Dung
Keywords: 離散小波轉換;有限資源排程理論;一維/二維離散小波處理器;離散小波矽智財元件;Discrete Wavelet Transform;DWT;Limited Resource Scheduling Alogrithm;Gerneric 1-D/2-D DWT Processor;DWT IP
Issue Date: 2000
Abstract: 近十年來,小波轉換被廣泛研究及應用在各個領域,如訊號/影像處理、語音壓縮/解壓縮、數值分析和碎形分析等等。小波轉換的硬體架構設計多是針對特定的小波系統,給予相當足夠的運算單元去對資料及運算作排程以減少儲存單元和增加硬體使用效率。然而,卻很少有人討論在系統晶片實現上的一個重要問題─有限資源實現。在本篇論文中,提出了有限資源小波轉換的排程理論,就濾波器長度、處理的資料量大小以及一維/二維小波轉換而言,可以彈性地處理不同的小波轉換運算。藉由排程理論所設計的硬體架構有高度的彈性、擴充性以及硬體使用效率。最後我們提出矽智財元件的概念,藉由一組系統參數去快速發展小波晶片。為了證明我們提出的排程理論與架構,我們具體實現了Db(9,7)小波晶片,內部使用了4個乘加器及兩個2048x16 bits的非同步靜態記憶體,在TSMC 0.35 1P4M CMOS的製程技術下,工作頻率可以達到50 MHz,每秒處理46張512x512大小影像,大約每秒可以處理11.5 M pixel的資料。
Wavelet transformations have become interesting to the signal processing society in the last decade. The Discrete Wavelet Transformation (DWT) has been employed in DSP applications such as signal analysis, image processing, numerical analysis, fractal analysis, and so on. Research of DWT implementation has focused on decreasing the storage size and increasing hardware utilization; however, very few papers deal with the limited-resource implementation. The limited-resource implementation is one of the most important issues in System-On-Chip (SOC) design. This thesis proposes a scheduling algorithm for limited-resource DWT implementation. The proposed scheduling algorithm can flexibly perform different DWT operations in terms of the length of FIR filters, the size of data blocks, and the dimension of wavelet transform. Using the scheduling algorithm the DWT implementation features high degree of flexibility, scalability, and hardware utilization. Finally, we propose an Intellectual Property (IP) generator to develop DWT chip based on a set of architectural parameters. To demonstrate the proposed DWT processor design we implement a Db(9,7) DWT IC using 4 MACs in TSMC 0.35 1P4M CMOS technology. As a result, the chip size is 3294.2 3288.6 , including standard cell area ( ), and two 2048 x 16 bits asynchronous sram macro area ( ). It can operate in 50 MHz, and perform 46 frames/sec with 512x512 pixel in 2-D DWT operation.
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