Title: 閘極二極體增益單元應用於低功率擬似靜態記憶體設計
Gated Diode Gain Cell for Low Power Pseudo SRAM Design
Authors: 鄭景允
Ching-Yun Cheng
Wei Hwang
Keywords: 低功率;擬似靜態記憶體;電源閘;增益單元;漏電流;low power;Pseudo SRAM;power gating;gain cell;standby leakage
Issue Date: 2005
Abstract: 本論文利用三顆電晶體和一顆二極體組成增益單元跟利用電源閘的技術來完成擬似靜態記憶體設計。閘極二極體因為有非線性的電容效應,所以當電壓被拉起時,若儲存資料是邏輯1,則電壓會被拉高,反之儲存資料是邏輯0則電壓還是會停留在低電位。利用這種會因為隨著內部儲存資料而產生極大的電壓增益,較大的訊號邊界和較強的電流驅動能力和低電壓記憶體均可以運作。閘極二極體的構造和它的訊號放大以及記憶體單元電路和陣列架構的細節都會在此論文呈現,然後和其它的記憶體單元做個比較。 接下來一個256行 × 32位元的三顆電晶體和一顆二極體增益單元陣列會在台積電 0.13um 製程下被實現並以它為例,並且將它應用在擬似靜態記憶體設計。多分區的擬似靜態記憶體每個都有各自獨立的存取控制電路,所以可以允許在不同分區作充電和讀-寫的並行處理。 然而三顆電晶體和一顆二極體增益單元也是一個需要週期性充電來維持它資料的正確性。所以會有一個方法和機制會被應用在任何情況下充電的行為都不會妨礙到外部存取。除此之外,由於CMOS製程已經進步到深次微米甚至奈米的時代,漏電流的問題也隨著臨界電壓及元件尺寸的降低而日益嚴重。因此我們將電源閘技術應用在三顆電晶體和一顆二極體的陣列的感應放大器上,可以減少它在睡眠模式中15%的漏電流和增加在正常模式中12%的感應速度。但會有少量的動態功率負擔。此結果是利用台積電 100 nm 技術模擬得到的結果。
The low-power Pseudo SRAM design with 3T1D gain cell and power-gating technique are realized in this thesis. The gated diode acts as a nonlinear capacitance for voltage boosting, where voltage for 1-data is boosted high and voltage for 0-data stays low, achieving significant voltage gain of the internal stored voltage, higher signal margin, higher current drive and low-voltage memory operation. Details about the gated diode structure, its signal amplification, the memory cell circuits and the array structure are presented, followed by comparison to other memory cells. Then 256-word x 32-bit 3T1D gain cell array is implemented in standard logic technology with TSMC 0.13um model for example, applying it to Pseudo-SRAM design. The multi-bank of Pseudo SRAM each has its independent access control circuit, enabling parallel refresh and read-write accesses to different bank. However, 3T1D gain cell is a DRAM cell which needs periodic refresh data for its correct function. Thus one method and apparatus is applied that refresh operation does not interfere with the external accesses under any conditions. In addition, as technology scale down to deep-submicron and nano-scale eras, the leakage current becomes more serious due to lower threshold voltage and smaller size transistor devices. Thus power-gating technique in SA of 3T1D array could reduce 15% standby leakage current during sleep mode and increasing 12% sensing speed during normal mode. But there will be some dynamic power overhead. It is simulated with TSMC 100nm technology model.
Appears in Collections:Thesis