Title: 應用DSMC法模擬垂直式旋轉基版LPCVD之熱流場及薄膜沈積The Simulation of Thermal Flow Field and Film Deposition in Vertical Rotating Substrate for LPCVD Using DSMC Method Authors: 蕭啟宏Chi-Hong Hsiao陳俊勳Chiun-Hsun Chen機械工程學系 Keywords: 低壓化學氣相沈積;直接模擬蒙地卡羅法;銅;平行處理;LPCVD;DSMC;Cu;Parallel computing Issue Date: 2000 Abstract: 本研究使用直接模擬蒙地卡羅法(Direct Simulation Monte Carlo method, DSMC) 模擬垂直式旋轉基座 LPCVD 反應腔體內之熱流場模式。本文主要分為三方面的探討：(一) 更新邊界條件來解決戴家宏論文中的缺點；(二) 增加新的設計參數，如 進口半徑、重力、腔壁溫度；(三) 應用平行處理軟體 (MPI) 來作平行運算。 在不同設計參數的影響方面，縮短入口跟基板間的距離可以提高平均沉積率並且得到較佳的沉積均勻度。此外，發現在提高腔體壓力、進口流率、基板溫度、腔壁溫度都可以增加上基板上的平均沉積率，但是會得到較差的沉積均勻度。在進口放置跟出口面積一樣大的環型檔板可以增加沉積的均勻度，但是會降低沉積率。旋轉基板可以得到較佳的沉積均勻度而且不影響沉積率。增加銅源含量則可以增加沉積率而且不會影響沉積均勻度。至於在計算重力對腔體沉積和沉積率的影響時，結果發現重力項對低壓環境的影響並不明顯。最後，在 DSMC 中計算輸出資料的平行程式已經完成，應用在四吋基板的腔體，一個計算程序可以節省0.23秒，應用在八吋基板則可以節省0.97秒。This thesis analyzes the flow and thermal field in a vertical LPCVD chamber with rotating susceptor by using DSMC method. It aims at the remodeling of boundary conditions to eliminate the shortcoming in Dei’s work [1], the extra design parameters, such as inlet tube diameter, gravity, and side-wall temperature and an application of parallel computation. For the different design parameters, the predicted results show that a higher average deposition rate and better uniformity can be achieved by shortening the distance between inlet and substrate. It leads to a better deposition rate but a poorer uniformity by increasing the operating pressure, inlet flow, substrate temperature and side wall temperature, respectively. Putting an annular baffle, whose width is equal to the one of outlet area in inlet area, results in a better uniformity but a poorer deposition rate. Rotating the susceptor will improve the uniformity without affecting the deposition rate. Increasing the percentage of reactant, Cu, can raise the deposition rate without affecting the uniformity. The gravity orientation has insignificant effect on the uniformity and deposition rate of LPCVD. The parallelization of DSMC is done in output process only. The saving times, 0.23 second and 0.97 second, are for 4-inch and 8-inch wafer computations, respectively. URI: http://140.113.39.130/cdrfb3/record/nctu/#NT890489078http://hdl.handle.net/11536/67578 Appears in Collections: Thesis