標題: 互補式金氧半十位元40MHz取樣頻率導管式類比數位轉換器
A 3.3v 10-bit CMOS pipelined Analog-to-Digital Converter
作者: 黃傑忠
Jie-Jueng Huang
吳錦川
Jiin-Chuan Wu
電子研究所
關鍵字: 類比數位轉換器;導管式;取樣頻率;ADC;pipelined;sampling rate
公開日期: 2005
摘要: 由於導管式類比數位轉換器在達到低功率且高速的同時,也不會耗費太大的面積,因此時常被使用在許多必須兼顧高速以及高精確度的應用中。然而如果想要達到更高速以及更高精確度的同時,許多的問題就會產生,像是電容的不匹配效應,運算放大器的有限增益以及頻寬,比較器的參考電壓漂移等等的問題。在本篇論文中,我們提出了一個新的正回授放大器來解決因增益與頻寬不夠還有寄生電容所造成的一些誤差,非常適用於高效能的類比數位轉換器中。 在這篇論文中,使用了台積電0.35um 雙氧化層以及四層金屬的製程來模擬一個全差動架構,3.3伏特供應電壓,10位元,40MHz 取樣頻率的類比數位轉換器,本設計採用了每級1.5位元的錯誤更正技術。這個類比數位轉換器中包含許多元件,其中有餘數放大器,比較器,正反器,加法器,時脈產生器和一個前端的取樣電路,此架構的差動輸入範圍是負1伏到正1伏。
Among all architectures of analog-to-digital converter (ADC), the pipeline architecture was widely used in applications with high speed and high resolution, due to its small size and low power consumption. If we want to achieve higher speed and more accuracy, there are some errors to overcome. Such as capacitor mismatch, operational amplifier gain error, bandwidth limitation, comparator threshold offset and so on. In this thesis, we present a new operational amplifier with positive feedback technique to reduce its gain error and input parasitic capacitance, it is well suited to implement ADC with high performance. In this thesis, a fully differential 3.3V, 10-bit, 40M sample/sec pipelined ADC with a 1.5-bit stage digital error correction has been designed with TSMC 0.35-μm double-poly four-metal CMOS process. The components in this ADC include residue amplifier, comparator, flip-flop, adder, clock generator and front-end sample-and-hold(S/H). The input range is -1V~+1V.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009211667
http://hdl.handle.net/11536/67446
Appears in Collections:Thesis


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