Title: 鎖相介質諧振腔振盪器
Phase-Locked Dielectric Resonator
Authors: 黃俊盛
Huang Chun Sheng
Chi-Yang Chang
Keywords: PLL;PLDRO;鎖相迴路;鎖相介質諧振腔振盪器
Issue Date: 2000
Abstract: 本論文說明微波電路中鎖相介質諧振腔震盪器的設計流程,其中包括相位檢測器,迴路濾波器,和壓控震盪器的製作.本論文將說明將相位雜訊作最佳化的方法,並說明如何得到迴路的穩定,本鎖相迴路介質諧振腔振盪器的壓控震盪器設計在6.25GHz,輸出功率微8.5dBm,適當的調正介質諧振腔的位址,將可得到在100kHz的頻率偏移量下相位雜訊為120dBc/Hz,最後將以量測的圖說明在迴路頻寬內的相位雜訊特性
This thessi presents a design process of plase-locked dielectric resonator oscillator (PLDRO) for millimeter-wave application,which includes the design of phase detector,loop filter and voltage controlled oscillator(VCO). Accurately transforming the impedance between reference source and SRD can get larger DC voltage at the output of phase detector.The larger voltage can help PLL to lock easily.This thesis also shows the method to optimize the phase noise of PLL and how to get stability of th loop.The voltage controlled dielectric resonator oscillator (VCDRO) in this PLDRO operates at 6.35GHz with output power of 8.5dBm.The tuning range of this VCDRO is 15MHz.Carefully choosing the position of DR in VCDRO can get excellent phase noise of 120dBc/Hz at 100k offset .Finally ,we also show the characteristics of phase noise inside the loop bandwidth by the measurement result.
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