Flat-band Voltage Stability of Metal Gate MOS devices
This thesis investigated the work function adjustability of TaNx films and the flat-band voltage stability of TaN-, Ta-, and Pt-gate MOS devices. The Cu barrier of TaNx films is also examined. The TaNx films were deposited by reactive sputtering in different ambient argon-nitrogen mixtures, with different Ar/N2 ratios; Ta and Pt films were deposited in pure Ar mass ambient. Samples with metal/SiO2/Si structures annealed at different temperatures in furnace in N2 ambient were used to analyze the thermal stability of the flat-band voltage. Several important features were observed and the guidelines for choosing metal gate materials were derived. The work function increases from 4.14eV to 4.21eV as the N/Ta ratio increases from 0.3 to 0.65. The range is small. Restated, TaNx is fit for use as a gate material in nMOSFET. Ta3N5 phase forms following a thermal process at 400℃ if the N/Ta ratio is as high as 0.65. This phase obviously increases in terms of resistivity When the N/Ta ratio is lower than 0.5, the resistivity remains stable up to 800℃. After annealing at temperatures higher than or equal to 600℃, copper diffuses into the substrate. The flatband voltage is significantly degraded by thermal stress and Cu ions. The highest sustainable process temperature after Cu/TaNx deposition is about 500℃. The work function of the Ta film is about 4.57eV. The flat-band voltage deviations of samples annealed at 400 to 800℃ are all below 23mV. In thermal annealing at above 600℃, Ta interacts with SiO2 to form a Ta-O compound and the flat-band voltage is seriously degraded by the thermal stress. The process temperature of the Ta gate should be approximately 500℃. The work function of the Pt film is about 5.38eV. Pt film is thermally stable up to 800℃. However, the high thermal stress generates many interface states and fixed charges, leading to a flat-band voltage variation of more than 0.57V. A flat-band voltage deviation as high as 600mV was also observed after thermal annealing at 600℃. Pt is not suitable for use as a gate electrode of MOS devices because of its high work function and high thermal stress. According to the ITRS roadmap, the 3σ variation of threshold voltage must be lower than 25mV following a 0.07μm technology node. The small flat-band voltage deviation creates an additional criterion for choosing the metal gate material and the integration scheme. Films with amorphous structures, negligible grain growth, and a negligible phase transformation at high temperature are preferred to eliminate deviation for metal gate materials. The highest process temperature is also determined by the stress induced flat-band voltage variation and deviation.
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