Title: 利用汲極崩潰熱電子注入操作的快閃式記憶體元件性能及可靠性研究
Performance and Reliability Studies of Flash Memories with Drain Avalanche Hot Electron Injection Scheme
Authors: 陳映仁
Yin Jen Chen
Steve S. Chung
Keywords: 快閃式記憶體;汲極崩潰;二氧化矽;熱電子;可靠性;操作模式;Flash Memory;Drain Avalanhe;SiO2;Hot Carrier;Reliability;operation scheme
Issue Date: 2000
Abstract: 近幾年來,快閃式記憶體(Flash Memory)已廣泛地應用於大量資料儲存上。過去,快閃式記憶體產品的設計多採用N通道快閃式記憶體元件。然而,為達到低功率消耗的快閃式記憶體,P通道快閃式記憶體元件將是另一種最佳的選擇。又因為元件的性能與可靠性是快閃式記憶體設計上的主要課題,然而以往的研究大多著重於發展新的元件結構,源極與汲極工程(Source/Drain Engineering),通道工程(Channel Engineering),以及改變元件的操作方式等。 本研究論文旨在提出一個新的快閃式記憶體元件設計方向,即是以浮動閘極工程來改善元件特性。其中,吾人針對不同浮動閘極P通道的快閃記憶體來進行特性的研究。根據實驗結果,並得出以下幾點結論。首先,我們比較N 和P型的浮動閘極之快閃式記憶體的性能。由於P型浮動閘極在寫入(抹除)操作時形成較高(低)的穿遂氧化層(Tunnel Oxide)電場,使其擁有較快的寫入速度卻較慢的抹除速度。其次,在耐久度(Endurance)測試上,N型與P型浮動閘極元件所得之特性幾乎一致。其次,吾人發現P型浮動閘極有較好的閘極擾動特性、較佳的讀取擾動特性與較大的半衰期容許電壓。尤其在汲極擾動的特性下,利用P型浮動閘極之P通道快閃記憶體有3個數量級的改善。而且,P型浮動閘極之快閃記憶體具也有較佳的資料流失(Intrinsic Charge Loss)特性。簡言之,從本研究結果可知,P通道P型浮動閘極之快閃記憶元件的結構有較多的優點,更適合應用於未來高可靠性(Reliability)快閃記憶體的產品設計。
Recently, the flash memory has become the main stream of nonvolatile semiconductor memory products. For the design of advanced flash memories, the performance and reliability are the major concerns. The design and improvement of flash memories are mainly focused on two approaches, one is to develop a novel cell structure, and the other one is to develop a different operation scheme. The most effective way to achieve a low power, low voltage and high speed operation requirements is through the help of a different operation scheme adopted in this thesis. In this thesis, first, the hot holes induced reliability studies is demonstrated for n-channel cells with Drain Avalanche Hot Electron (DAHE) programming . Then a comprehensive study of the programming schemes, the DAHE and the Band-to-Band induced Hot Electrons injection (BBHE), are applied to p-channel cells. From the experimental result, the hot holes enhanced device degradation can be observed when the control gate bias is too low to suppress the unwanted hot holes injection in n-channel cells during programming. On the other hand, the cells will suffer from the gate disturb if the control gate bias is too high. Therefore, a trade-off between the reliability and performance for the design of control gate bias with DAHE programming scheme is necessary. However, this kind of trade-off does not happen in p-channel cells. In terms of the performance in a p-channel cell, the DAHE has a faster programming speed owing to a large gate current by comparing with that of BBHE as a result of a smaller applied control gate bias. In terms of the cell reliability, the DAHE shows the better gate disturb characteristics than that of BBHE. Finally, the design concept of the triple well interconnection with an applied substrate bias is introduced to eliminate the drain disturb for both n-channel and p-channel cells based on the DAHE programming scheme.
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