Fabrication and Characterization of TiN-Gated CMOS Devices
|關鍵字:||金屬閘極;氮化鈦;熱穩定性;metal gate;TiN;thermal stability|
|摘要:||當CMOS 閘極長度微縮到 100 nm，其閘氧化層為超薄時，我們遇到了多晶矽空乏效應和高的閘極電阻等問題。金屬閘極的使用不失為解決這些問題的方法之一。本次實驗是採用以物理氣相沉積(PVD)方式成長的氮化鈦當金屬閘極，實驗主要是探討在汲極及源極的離子佈植完成之後，不同的熱預算對金屬閘極元件特性之影響，其中快速退火(RTA)的溫度分別是700°C、800°C、850°C、900°C及1000°C。
我們比較不同退火溫度時間對互補式金氧半電晶體元件特性的影響，發現相對於PMOS而言，NMOS元件需要高的退火溫度才能有效的降低接面漏電流。不同的熱預算不但會影響氧化層厚度、平帶電壓及電晶體的基本特性，還會影響氮化鈦金屬層的結構。此外，由於LOCOS邊緣寄生電晶體的存在，我們在PMOSFET元件的次臨界電流特性上發現電流有隆起(current hump)的情況；實驗中還發現高溫的退火製程，雖然能修補氧化層與基板界面的缺陷，但也會使金屬薄膜的熱穩定性退化，特別是在較窄的金屬線上，太高溫的製程使得閘極金屬發生結塊聚集(agglomeration phenomenon)的現象，進而使得元件的閘極漏電流上升。最後，我們看到電漿充電效應對金屬閘極元件造成嚴重的損害，是日後金屬閘極蝕刻所必須注意的問題。|
CMOS devices with metal-gate have recently received lots of attention owing to the low resistivity of metal layers and the capability of eliminating the ploy depletion effect (PDE) encountered in poly-gate counterparts. However, many process-related issues, such as the metal penetration, plasma damage, and impurity contamination, may limit practical applications of metal-gate CMOS. More efforts are thus required to improve the control of the processes as well as the device performance The effects of rapid-thermal annealing (RTA) after source/drain (S/D) implant on the characteristics of CMOS transistors with sputtered TiN gate were investigated. Our results indicate that n+/p junctions need higher thermal budget than p+/n junctions to achieve low leakage performance. It was also found that from C-V measurements, the flat-band voltage and oxide thickness are both affected by the annealing treatment, especially for p-channel devices. We thought that the F species in BF2+ implant tends to increase the oxide thickness of PMOS devices after RTA treatment. Also, a hump in the subthreshold characteristics of p-channel transistors is observed, owing to the existence of a leakage path along the isolation edge. It is also shown that agglomeration phenomenon is easier to incur during the high-temperature RTA step as the metal gate width becomes narrower. When this happens, gate oxide integrity would be degraded, resulting in increased gate leakage of n-channel transistors. Besides, the temperature dependences of gate leakage current and charge pumping current are in contrast. One possible explanation is that the increase in gate leakage after high-temperature is a localized conduction phenomenon, i.e., the leakage flows only through some localized spots, even the higher temperature annealing can repair the SiO2/Si interface.