Title: 具有蕭特基源/汲極能障SOI金氧半場效電晶體之製作與研究
Fabrication and Development of Schottky Source/Drain SOI MOSFET
Authors: 呂嘉裕
Chia-Yu Lu
Tiao-Yuan Huang
Horng-Chih Lin
Keywords: 蕭特基能障金氧半電晶體;金屬矽化;絕緣體上矽晶;雙極性元件;副閘極;負微分電導;Schottky barrier MOSFET;Silicide;SOI;ambipolar devices;sub-gate;negative differetial conductance
Issue Date: 2000
Abstract: 本篇論文是整合蕭特基源/汲極元件於SOI晶片上。因為蕭特基元件是以矽化金屬取代傳統離子佈值產生源/汲極的方式,所以具有製程簡單、適用於低溫製程步驟,以及可同時操作於n和p通道等優點。但是傳統蕭特基源/汲極元件由於天生金屬與半導體接面具有較大漏電流的現象,造成蕭特基元件具有大漏電流,進而減少其導通與關閉電流的比率,大大的扼殺了蕭特基電晶體的應用。 在本篇論文中,我們結合了所謂電壓產生延伸汲極(field-induced drain)的結構,此結構能夠有效的壓抑在汲極端所產生的高電場,而且因為延伸汲極的因素,使得元件通道與汲極間可視為如同一般半導體與半導體的接面,所以能有效的抑制大漏電流的現象,使得元件的特性更加理想。為了探討導通與關閉電流的比率,在此我們特地將元件的主閘極與次閘極的角色對換,做一連串長通道與短通道的比較實驗,得到對於n通道和p通道而言,導通與關閉電流的比率分別為1E6和1E8。因為本實驗是採用鎳金屬矽化源/汲極,鎳金屬矽化對於電子的蕭特基能障大約為0.7 eV,遠大於電洞的0.41 eV,所以大大的降低n通道的特性。 當對元件做輸出特性的量測,在接大的閘極和汲極電壓時,n通道元件會產生隨著汲極電壓增加而造成汲極電流減少,即所謂的Negative Differential Conductance (NDC)的現象,這是因為在源極產生的熱電子進入閘極氧化層,造成電子捕捉,使元件起始電壓上升,汲極電流減少的原因。在p通道元件由於電洞對二氧化矽的能障高約為4.7 eV,高於電子與二氧化矽的能障(3.2 eV),所以不易發生NDC的現象。未來我們將嘗試將此現象運用於非揮發性記憶體的寫入動作,若是能成功的運用將可為非揮發性記憶體注入一股新生命。
In this thesis, we have fabricated Schottky barrier (SB) MOSFET on SOI wafers. SB MOSFET employs silicide source/drain in lieu of ion implanted source/drain. So it is simple in processing, well suited for low temperature process. Further, it can operate both as n- and p-channel transistors (i.e., ambipolar). However, traditional SB MOSFET suffers from extremely large leakage current inherent in metal-semiconductor Schottky junction and therefore poor on/off current ratio, which severely restricted its application to mainstream integrated circuits. In this study, we have proposed and demonstrated new SB MOSFET devices that incorporated the field-induced-drain (FID) structure in an effort to reduce the large leakage current. Since FID can effectively reduce the high field in drain-side and induce the extension drain under the offset length, so the large leakage current can be effectively reduced and the device performance greatly improved. In order to understand on/off current ratio in more detail, we have investigated the effects of sub-gate bias and drain offset length on the resultant device characteristics. By studying devices with a series of long and short channels, we obtained the on/off current ratio for n- and p-channel devices to be 1E6 and 1E8, respectively. In this thesis, we used nickel silicide for source/drain. Since nickel silicide’s Schottky barrier height for electrons is about 0.7 eV larger than that for holes (0.41 eV), so the performance of n-channel operation is expected to be inferior to that of p-channel operation. In the output characteristics, when VG and VD are large, n-channel device appeared reduction of drain current, the so-called called negative differential conductance (NDC). This is believed to be due to the source-side hot electron injection, causing electron trapping in the gate oxide. The resultant threshold voltage increase causes a reduction in the drain current. NDC is not observed in the p-channel operation, because the barrier height of holes to oxide is 4.7 eV, which is larger than that of electrons to oxide (i.e., 3.2 eV). It is worth noting that NDC phenomenon, though undesirable for normal transistor operation, could be potentially utilized as an efficient programming source for future low-power non-volatile memory (NVM) applications.
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