Title: 適用於高低壓共容輸入輸出電路之靜電放電防護設計
ESD Protection Design for Mixed-Voltage I/O Circuits
Authors: 莊健暉
Chien-Hui Chaung
M.-D. Ker
Keywords: 高低壓;Mixed-Voltage
Issue Date: 2000
Abstract: 摘要 本論文提出針對改善高低壓輸入輸出電路中之堆疊電晶體的靜電放電防護能力的方法,分成兩部份來探討。 本論文的第一部份,利用基體觸發技術來提昇高低壓輸出入電路中之堆疊電晶體的靜電放電防護能力。由實驗的分析中可知,當利用基體觸發技術使基體電流增加時,高低壓輸入輸出電路中之堆疊電晶體的二次崩潰電流(It2)也會隨之增加。另外,利用基體觸發技術也可使高低壓輸入輸出電路中之堆疊電晶體的觸發電壓降低,如此更可以有效地保護高低壓輸入輸出電路。這種利用基體觸發技術的2.5V/3.3V共容高低壓輸入輸出電路的靜電放電防護電路已完成晶片製作,並已成功地驗證於0.25微米CMOS製程中。實驗結果顯示本論文所提出的設計可以有效提昇高低壓輸入輸出電路的靜電放電耐受能力達160%以上。 本論文的第二部份,另外提出一種新的靜電放電防護電路,利用堆疊電晶體觸發矽控整流器的元件當作靜電放電防護元件,來保護積體電路中的高低壓輸出入電路。這種堆疊電晶體觸發矽控整流器的元件,不需用厚的閘極氧化層,且因為具有較低的觸發電壓及維持電壓的特性,可明顯地提昇高低壓輸入輸出電路的靜電放電防護能力。這種提出的3.3V/5V共容高低壓輸入輸出電路的靜電放電防護電路已完成晶片製作驗證,並已成功地驗證於0.35微米CMOS製程中。由實驗的結果中可知,本論文所提出的高低壓輸入輸出電路的靜電放電防護電路,其人體放電靜電模型(HBM)的靜電放電耐受電壓可從2仟伏特提昇至8仟伏特。本論文之研發成果,已經提出三項美國專利申請,部份論文成果並已獲2001 EOS/ESD Symposium 國際研討會所接受。
ABSTRACT To improve ESD robustness of the stacked-NMOS device in the mixed-voltage I/O circuit, there are two new designs proposed in this thesis. In the first part, a substrate-triggering technique has been used to improve the protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. From the experimental measurement results, the second breakdown current (It2) of the substrate-triggered stacked-NMOS can be effectively increased when the substrate current is increased. The substrate-triggering technique can further lower the trigger voltage of the stacked-NMOS device to ensure effective protection for the mixed-voltage I/O circuit. The on-chip ESD protection circuit designed with the substrate-triggering technique for 2.5V/3.3V tolerant mixed-voltage IC has been fabricated and verified in a 0.25-µm salicide CMOS process. Experimental results have shown that the ESD robustness of the mixed-voltage I/O circuit can be improved 160% by this substrate-triggering design. In the second part, a new ESD protection circuit, by using the stacked-NMOS triggered silicon controlled rectifier (SNTSCR) as the ESD clamp device, is designed to protect the mixed-voltage I/O buffer of CMOS IC’s. Without using the thick gate oxide, the SNTSCR has a lower trigger voltage and a low holding voltage to effectively protect the mixed-voltage I/O circuits with an improved ESD level. The proposed ESD protection circuit has been verified for 3.3V/5V tolerant mixed-voltage IC in a 0.35-µm CMOS process. Experimental results have proven that the HBM ESD level of the mixed-voltage I/O buffer can be successfully increased from the original ~2kV to become 8kV by using this new ESD protection circuit. The research results of this thesis have been applied 3 U.S. patents, and a paper has been accepted by the 2001 EOS/ESD Symposium.
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