Study on the Measurement Design and Device Characteristics of Power MOSFET
|Keywords:||功率電晶體;安全工作區;崩潰能力;Power MOSFET;Safe Operating Area;Avalanche capability;Unclamped inductive switching;gate charge|
|Abstract:||在現今生活中，功率金氧半電晶體(Power MOSFET)的應用十分廣泛，諸如電源供應器、顯示驅動電路、及汽車電子等；因此，對於其在操作時可能受到之高應力(High stress )環境下之可靠性研究，日顯重要。
本論文將針對功率金氧半電晶體之閘極電荷特性(Gate charge characteristics)、順向偏壓安全工作區(Forward biased safe operating area)及崩潰能力(Avalanche capability)作深入之探討，並建立其相關之測試環境電路。
在閘極特性研究中顯示，元件工作在較高之汲極電壓和汲極電流下，將須較多之閘極電荷，且切換延遲時間也較長。而對於順向偏壓安全工作區之研究中指出，安全工作區的範圍決定在導通阻值(On state resistance)、最大額定電流(Maximum rated current)、最大固定功率損耗(Maximum constant power dissipation)、不穩定熱效應(Thermal instability effect)、及雪崩崩潰現象(Avalanche breakdown)。且在高汲極電壓且低汲極電流的工作絛件下，我們發現到一個類似二次崩潰(Second breakdown)之不正常損壞現象發生，此現象被證實是因為熱不穩定效應而導致之電流聚集現象所致。
接著，為了要評估元件之崩潰能力，我們採用了非箝制電感性切換測試電路(Unclamped inductive switching test)；研究結果顯示，崩潰損壞的原因不是由於自我加熱效應(Self heating)，而是導因於寄生雙極性電晶體的導通；於是，我們利用MEDICITM軟體作一系列的製程參數模擬，以來驗證所提出之崩潰模型(Avalanche model)。最後，並提出了一個改良型之功率金氧半電晶體，且由實驗證實其在崩潰能力上確有很大之改進。|
The widespread usage of power MOSFETs in diverse applications, nowadays, demands a better knowledge about the reliability of these devices under high stress conditions. To characterize this ‘ruggedness’ and for optimizing the design for better reliability under high stress conditions, comprehensive studies on the gate charge characteristics, forward biased safe operating area (FBSOA) and the avalanche capability of power MOSFETs are investigated in this thesis. The test circuits for the various measurements in our experiments have been built up. In the case of gate charge test, the higher value of gate charge is found in the operation of higher drain current and drain voltage. The longer switching delay time is also observed. In the study of forward biased safe operating area (FBSOA), it is demonstrated that the safe operating boundary is determined by the on state resistance RDS(ON), the maximum rated current IDM , the maximum constant power dissipation PMAX, the thermal instability effect, and the avalanche breakdown voltage in the new generation trench gate power MOSFETs. An anomalous failure, looking similar to second breakdown, in the high voltage and low current operation is detected. This undesired effect is shown to result from the current focusing phenomena caused by the thermal instability of the device. Unclamped inductive switching (UIS) is employed to characterize the avalanche capability of the device. It is demonstrated that the avalanche failure is not caused by the self-heating effect but the turning-on of the parasitic bipolar transistor. Extended simulations with MEDICITM were carried out to verify the proposed avalanche model. Great dependence of avalanche capability on process stability was also detected. Finally, a modified improved power MOSFET was devised and shown to have a great avalanche capability.
|Appears in Collections:||Thesis|