Title: 應用遞昇結構於二維數位小波轉換且具行式產出、高記憶體效能並可程式化特性的硬體架構
A Lined-Based, Memory Efficient and Programmable Architecture for 2D DWT using Lifting Scheme
Authors: 張偉信
Wei-Hsin Chang
Chen-Yi Lee
Keywords: 數位小波轉換;小波;JPEG2000;DWT;wavelet;JPEG2000
Issue Date: 2000
Abstract: 在過去的十幾年間,隨著小波理論的發展,數位小波轉換在許多領域扮演著重要的角色,諸如影像壓縮、語音處理、樣型辨識、數位視訊處理、雜訊消除以及材質辨別等。由於廣泛的應用領域以及較高的計算複雜度,專為數位小波轉換設計的硬體架構也就顯得更為重要。 在本論文中,首先我們將對小波的基本理論以及其在影像壓縮上的應用做簡單的介紹。接下來則是對於遞昇架構的描述以及我們所提出的「利用遞昇架構的小波轉換硬體架構」。並且利用一個稱為 SystemC 的新系統層級模擬方法來測試我們的架構。最後,我們提出了與其他類似架構的比較以說明本論文的貢獻。
During the last decade, with the progress of wavelet theory, discrete wavelet transform (DWT) plays an significant role in numerous fields such as image compression, speech processing, pattern recognition, digital video processing, noise removal, texture discrimination and so on. With the large application domain and higher calculation, the study of specified VLSI implementation for DWT becomes more important. In this thesis, first, we will make an introduction to the basic theory of wavelet transform and its applications in image processing. Second, the foundation of lifting scheme is described. To follow, our architecture using lifting scheme is proposed. The simulation of our architecture is based on SystemC, which is a new method of system level simulation. And in the last, comparison to other design is made to highlight the contribution of this thesis.
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