Title: 利用 TI TMS320C62xx 即時實現通道編碼及 H.263+ 編解碼器
Real-time Implementation of Channel Coding and H.263+ Coder Using TI TMS320C62xx
Authors: 施圭聰
Kuei-tsung Shih
Hsueh-Ming Hang
Keywords: 通道編碼;視訊編碼;3GPP;H.263;DSP
Issue Date: 2000
Abstract: 在多雜訊的無線通道上,通道編碼對於傳遞資料的保護扮演著不可或缺的重要角色。本篇論文評估了3GPP通道編碼的效能,並利用市面上既有的數位訊號處理器,實現一個通道編碼系統,期望能達到即時工作的目標。除此之外,我們還修改之前實現的H.263+視訊編解碼器,目的是使經過編碼後的相片畫質能夠得到改善。我們所實現的即時系統都採用德州儀器的TMS320C62xx,是一個定點運算且具有強大數位訊號處理功能的處理器。 我們簡單地介紹了3GPP的兩種通道編碼:迴旋編碼和渦輪編碼。因為前者涵蓋較低的複雜度,所以我們選擇前者來實現我們的即時系統。我們引用了兩種通道錯誤模型來評估迴旋編碼的除錯能力。他們分別是加成性高斯雜訊模型和雷利衰弱通道(吉爾伯模型)。在迴旋編碼的解碼上,我們採用的是削去式Viterbi演算法。我們首先設計一個系統流程,然後寫一個C程式來確認流程中每個區塊的正確性。最後我們依據數位訊號處理器的特性和運算能力,對我們的程式加以修改,以期有效的利用硬體資源。我們的迴旋編碼器每秒可以編碼超過1 M的資料,而Viterbi解碼器只能解碼9.57 K的資料。 再者,我們也對H.263+作了簡短的介紹。在之前實現的即時系統中,我們使用了鑽石型搜尋和一個定點的DIF DCT來減少整個編碼器的運算複雜度,而在這個定點DCT中所作的四捨五入動作,卻使得經過編碼的相片畫質降低。我們試著利用在H.263+附錄W中所定義的定點DCT來替換原有的DCT,並且利用H.263+附錄A所提供的方法來比較這兩個DCT的精確度。雖然利用附錄W提供的DCT能夠使經過編碼的相片畫質提高,但整個即時系統的速度卻降低了。整個系統的編解碼流程只在一顆數位訊號處理器上運作時,每秒鐘能夠處理的圖形從原來的15張降低為9張。
Over noisy wireless channel, channel coding plays a essential role for protecting the transmitted data. In this thesis, we evaluate the performance of channel coding in 3GPP and complete a real-time implementation on a digital signal processor (DSP). Furthermore, we revise our previous implementation of H.263+ video coder for the purpose of improving the quality of encoded pictures. Both implementations use the TI TMS320C62xx, a powerful processor with fixed-point arithmetic. We briefly introduce two channel coding schemes in 3GPP, convolutional coding and turbo coding. We adopt the former in our implementation because it is less complicated. To evaluate the ability of convolutional codes, we use two channel error models. They are Additive White Gaussian Noise (AWGN) channel and Rayleigh fading channel (Gilbert model). For decoding the convolutional codes, we use truncated Viterbi algorithm. We design a function flow at first and then verify the functionalities by building an ANSI C program. Finally, we refine our codes by taking advantages of the DSP architecture and computation power to produce an efficient program. Overall, our convolutional encoder can handle more than 1 Mbps, while our Viterbi decoder can handle only 9.57 Kbps. We also give a short introduction to H.263+. In our previous implementation, we use the diamond search and a fixed-point DIF DCT to reduce the computation complexity of the entire codec. Rounding errors due to the DCT reduce the quality of encoded pictures. We try to use the fixed-point DCT defined in H.623+ Annex W for an alternative. We use the methodology supported in H.263+ Annex A to compare accuracy of these two DCT algorithms. Though adopting the DCT in Annex W provides better quality of encoded pictures, the video coder suffers speed degradation. The entire system using one DSP for both encoding and decoding processes only 9 frames per second, instead of 15 frames per second originally.
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