標題: 1.6 Gbps 更低擺幅差動訊號傳輸之傳送器
A 1.6Gbps RSDS Serial-Link Transceiver
作者: 鍾竣帆
Chung Chun Fan
吳錦川
Jiin-Chuan Wu
電子研究所
關鍵字: 更低擺幅;傳送器;鎖相迴路;高速串列數位影像傳輸介面;虛擬隨機位元串列產生器;RSDS;Transceiver;PLL;high-speed serial link I/O interface;PRBS
公開日期: 2005
摘要: 隨著積體電路製程技術的進步,對於需要高頻寬和低延遲晶片之間資料傳輸也隨之增加,傳輸介面的電路所能達到的單位時間最大傳輸量往往是整體系統速度的關鍵限制。 本篇論文是描述一個應用於高速串列數位影像傳輸介面,使用低擺幅差動訊號傳輸之傳送器的設計,並致力於設計兩種資料傳輸速度操作在 1.6Gbps的傳送器,這兩種傳輸器的差別在於傳輸時脈的不同,第一種傳輸器傳100MHz的時脈,第二種傳800MHz的時脈。 傳送器由一個八相位鎖相迴路、虛擬隨機位元串列產生器、四對一多工器、時脈處理電路、輸出資料和時脈驅動器所組成,其中,八相位鎖相迴路的輸入頻率為400MHz,輸出為八個相位,平均分佈且頻率同為400 MHz的時脈訊號,所包含的電路有相位/頻率偵測器、電荷幫浦、迴路濾波器、四級差動壓控振盪器和一個除四的除頻器。此鎖相迴路所產生的平均分佈時脈提供給虛擬隨機位元串列產生器和四對一多工器,並將一組並列資料轉為串列輸出,時脈處理電路將時脈處裡過後,最後,將此時脈及串列資料傳送至傳輸線上,即完成整個傳送器的設計。 接收器使用具有磁滯現象的比較器將傳送過來的資料和時脈放大成數位訊號。然後,第一種接受器使用100MHz產生平均分佈且頻率同為400 MHz的時脈訊號來取值, 第二種接受器使用輸入資料頻率一半的時脈800MHz來取值。最後,解多工器將時脈資料回復電路的輸出轉變成八個平行資料通道。
As the IC fabrication technology advances, the need for high-bandwidth and low-latency inter-chip data transfer has also increased. Most of time, the key limitation of a whole system is the maximum data amounts of the transmission interface circuit transmitted in each unit time. This thesis describes the design of a high-speed serial link I/O interface. We have devoted to design two types of the transceiver at 1.6Gbps.The difference between Type 1 transceiver and Type 2 transceiver is the frequency of the output clock. Type 1 transceiver transfers 100MHz clock; Type 2 transceiver transfers 800MHz clock. The transmitter is composed of a eight-phase PLL, PRBS circuits, 4-1 multiplexers, clock process circuit and an output data and clock driver. Among these devices, the input frequency of the eight-phase PLL is 100MHz, and it outputs eight uniformly distributed clocks with 400 GHz frequency. The PLL consists of a Phase/Frequency Detector, a Charge Pump, a Loop Filter, a four-stage differential VCO and a divided-by-four divider. It offers the PRBS and the 4-1 multiplexer with four uniformly distributed clocks to convert parallel pseudo-data into serial stream. Then, the serial data is transmitted by an output data driver. In the end, the transmitter drives the serial data and clock onto the transmission bus. The receiver uses the comparator with hysteresis to amplify the incoming data and clock to full swing. Then, Type 1 receiver uses 100MHz clock to generate four uniformly distributed clocks with 400 GHz frequency to sample data. Type 2 receiver uses 800MHz operating at half of the input data rate Finally, the de-multiplexer converts the serial outputs to four parallel data channels.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009211632
http://hdl.handle.net/11536/67090
Appears in Collections:Thesis


Files in This Item:

  1. 163201.pdf