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dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorLin, Chien-Chingen_US
dc.contributor.authorChang, Fu-Keen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2014-12-08T15:08:46Z-
dc.date.available2014-12-08T15:08:46Z-
dc.date.issued2009-09-01en_US
dc.identifier.issn1549-8328en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2008.2010143en_US
dc.identifier.urihttp://hdl.handle.net/11536/6706-
dc.description.abstractThis paper presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers in the universal syndrome calculator and Chien search block, as well as an on-the-fly inversion table for calculating error or errata values. After implemented with 0.18-mu m 1P6M technology, the proposed universal RS decoder correcting up to 16 errors can be measured to reach a maximum 1.28 Gb/s data rate at 160 MHz. The total gates count is around 46.4 K with 1.21 mm silicon area, and the average core power consumption is 68.1 mW.en_US
dc.language.isoen_USen_US
dc.subjectError-and-erasure correctionen_US
dc.subjectMontgomery multiplicationen_US
dc.subjectReed-Solomon (RS) codeen_US
dc.subjectuniversal architectureen_US
dc.titleA Universal VLSI Architecture for ReedSolomon Error-and-Erasure Decodersen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSI.2008.2010143en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERSen_US
dc.citation.volume56en_US
dc.citation.issue9en_US
dc.citation.spage1960en_US
dc.citation.epage1967en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000269684600001-
dc.citation.woscount1-
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