標題: A Universal VLSI Architecture for ReedSolomon Error-and-Erasure Decoders
作者: Chang, Hsie-Chia
Lin, Chien-Ching
Chang, Fu-Ke
Lee, Chen-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Error-and-erasure correction;Montgomery multiplication;Reed-Solomon (RS) code;universal architecture
公開日期: 1-Sep-2009
摘要: This paper presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers in the universal syndrome calculator and Chien search block, as well as an on-the-fly inversion table for calculating error or errata values. After implemented with 0.18-mu m 1P6M technology, the proposed universal RS decoder correcting up to 16 errors can be measured to reach a maximum 1.28 Gb/s data rate at 160 MHz. The total gates count is around 46.4 K with 1.21 mm silicon area, and the average core power consumption is 68.1 mW.
URI: http://dx.doi.org/10.1109/TCSI.2008.2010143
http://hdl.handle.net/11536/6706
ISSN: 1549-8328
DOI: 10.1109/TCSI.2008.2010143
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 56
Issue: 9
起始頁: 1960
結束頁: 1967
Appears in Collections:Articles


Files in This Item:

  1. 000269684600001.pdf