標題: 低壓差動訊號標準(LVDS)之平面顯示器高速傳送器設計
Design on 1.225 Gbps LVDS Transmitter for UXGA Flat Panel Display Applications
作者: 周宗信
柯明道
電子研究所
關鍵字: 低壓差動訊號標準;平面顯示器;傳送器;LVDS;FPD;transmitter;serial-link
公開日期: 2004
摘要: 隨著製程的進步,不僅是積體電路上的電路複雜度更高且速度也隨之提升。因此對於一個高效能的系統,高頻寬、低功率的傳輸介面也就更加需要。而在今日的平面顯示器,其色彩及解析度的要求越來越高。而對一個UXGA (1600 × 1200)解析度的顯示器來說,其所需要的資料傳輸速度至少必須在1.155 Gb/s以上。在此篇論文,包含兩個設計子項,並經由兩個獨立晶片來驗証。 第一個設計是PLL。使用的製程是0.13-μm 1P8M CMOS。使用的電壓是3.3V,而並沒有除頻。 第二個設計則傳送器的設計包含一個可把7位元轉換成一個低壓差動訊號的資料外,並且也提供了一個時序信號。同樣是在0.13-μm 1P7M CMOS包含PRBS作為內部測試的訊號源。傳送器能正常傳送出1.4 Gb/s的串列資料。在電壓電源為3.3V時,總消耗功率為125mW。
With the advanced process technology, the complexity and the operating speed of the circuit are increasing. Therefore, for a system with high performance, a high data-bandwidth and low power transmission interface is very important nowadays. Flat panel displays (FPDs) continue to offer an increase in color depth and resolution, today. For UXGA (1600 × 1200) resolution required by flat panel display system, the data transmission rate must be higher than 1.155 Gb/s. This thesis includes two topics, which were verified through two individual chips. The first design is the PLL, implemented on the process of 0.13-μm 1P8M CMOS. The operating voltage is 3.3V and the frequency division is not included. The second design is the transmitter, which includes one data channel, converting seven bits into one data stream, and one clock channel. The circuit is implemented with the process of 0.13-μm 1P8M CMOS. It also includes a PRBS as a self-test signal source. The transmitter can transmit 1.4 GB/s serial data stream properly. The power consumption is about 125mW at 3.3V.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009211629
http://hdl.handle.net/11536/67057
Appears in Collections:Thesis


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  1. 162901.pdf