標題: 複晶矽薄膜電晶體之製程與可靠度之研究
Study on the Process and Reliability of Poly-Si Thin-Film Transistors
作者: 桑任逸
Jen-Yi Sang
雷添福
Tan-Fu Lei
電子研究所
關鍵字: 複晶矽薄膜電晶體;可靠度;摻氟矽玻璃;多重通道;雙極性接面電晶體效應;poly-Si TFT;reliability;FSG;multi-channel;parasitic BJT
公開日期: 2004
摘要: 在本論文中,首先,我們提出在摻氟矽玻璃(FSG)上製造的複晶矽薄膜電晶體。實驗結果顯示元件的電特性和均勻度可藉由摻雜適量的氟原子達到明顯的改善。與傳統複晶矽薄膜電晶體相較之下,製造在摻氟矽玻璃上的複晶矽薄膜電晶體具有較高的導通電流及場效遷移率,並使得漏電流降低。這是因為氟原子能修補複晶矽與絕緣層介面處及位於通道中複晶矽晶格邊界的缺陷。再者,由於氟與矽原子可形成較強的鍵結,經過熱載子應力(hot carrier stress)測試後,發現摻入氟原子的複晶矽薄膜電晶體具有較好的可靠度。 接著,我們進行有關多重通道(multi-channel)複晶矽薄膜電晶體的研究。藉由增加通道的數目來提高閘極的控制能力,可以改善元件的電特性;包括提高導通電流,降低臨界電壓(threshold voltage)及次臨限擺幅(subthreshold swing)。然而,元件的可靠度卻會因此而變差。我們推測是由於在多重通道的結構中,靠近汲極端的電場強度會增加,而導致更嚴重的碰撞游離(impact ionization)所造成。 最後,我們探討有關複晶矽薄膜電晶體生命週期(lifetime)的問題。發現到最糟的熱載子應力測試條件是在閘極電壓大約等於臨界電壓的情形下,而非傳統上閘極電壓等於二分之一汲極電壓。此外,亦發現到在高的汲極電壓(drain voltage)應力測試條件下,導通電流隨時間的劣化具有相同的斜率,生命週期的分佈亦呈線性關係,因為在此情形下元件的傷害主要是由碰撞游離(impact ionization)所造成。然而,在低的汲極電壓(drain voltage)測試條件下會有不同的現象發生。這是因為此時必須考慮寄生雙極性接面電晶體效應(parasitic bipolar junction transistor action)。
In this thesis, first, a process-compatible scheme for fabricating poly-Si TFTs on an FSG buffer layer was proposed and demonstrated. Experimental results reveal that remarkably improved device performance and uniformity can be achieved with appropriate fluorine concentration. The poly-Si TFT fabricated on FSG layers has a higher on-current, a lower leakage current, and a higher field-effect mobility compared with the conventional poly-Si TFT. The fluorine atoms can passivate the Si/SiO2 interface states and grain boundary trap states in the poly-Si. Furthermore, the incorporation of fluorine also increases the reliability of poly-Si TFTs against hot carrier stressing, which is attributed to due to the formation of the rather strong Si-F bonds. Then, Multi-channel poly-Si TFTs were studied. The device’s electrical characteristic such as on-current, threshold voltage, and subthreshold swing were improved with increasing the channel stripes due to the enhancement of gate control capability. However, the device’s reliability was deteriorated. We concluded that electric field strength near the drain side was enlarged in multi-channel structure, causing severer impact ionization. Finally, we studied the lifetime issue of poly-Si TFTs. It was found that the worst-case of stress conditions is under VG□Vth, not VG=1/2 VD. Moreover, it is revealed that under high VD of stress conditions, the Ion degradation has the same slope with stress time and the lifetime distribution has a linear relationship due to impact ionization dominating. However, under low VD, it shows a different phenomenon. We concluded that the parasitic BJT should be considered in these stress conditions.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009211535
http://hdl.handle.net/11536/66057
Appears in Collections:Thesis


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