Investigation of Hot Carrier Stress-Induced Oxide Reliability Issues in Deep-Submicron CMOS Devices
|關鍵字:||熱載子效應;氧化層可靠度;氧化層缺陷空間分布;汲極漏電流;次臨界電流的突起;歐傑再結合增強電子能量機制;價帶電子穿隧;快閃式記憶體寫入方法;hot carrier effect;oxide reliability;oxide trap spatial distribution;drain leakage current;subthreshold current hump;Auger recombination enhanced electron energy gain process;valence-band electron tunneling;programming technique in flash EEPROMs|
接下來，吾人發現元件在動態臨界電壓場效電晶體(DTMOS)操作模式下會有增強熱載子退化，而此現象無法用傳統熱載子理論解釋。因此吾人提出一歐傑再結合(Auger recombination)增強電子能量機制。吾人利用熱載子激光與熱載子閘極電流入射實驗來證明通道中電子能量因正偏基極引發電洞入射產生歐傑再結合效應而增加。根據研究結果顯示，在此操作模式下汲極電流與汲極雜訊(noise)退化較傳統熱載子操作下更嚴重。不同於傳統熱載子所造成的元件退化，歐傑再結合所造成元件退化和溫度成正相關，因此對於在高溫操作的先進元件會有更嚴重的可靠性問題。同時吾人也觀察在超薄氧化層元件中因價帶電子穿隧(valence-band electron tunneling)所引發的歐傑再結合增強熱載子退化，此增強退化現象和基極電壓成正相關，因此對於SOI和DTMOS元件將會造成嚴重的可靠性問題。
This dissertation addresses the issues related to hot carrier effects in CMOS devices. First, an oxide trap characterization technique by measuring a subthreshold current transient is developed. This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps. Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized. By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained. Our results show that (1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, (2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and (3) the hot hole stress created oxide charges exhibits a shortest effective detrapping time-constant. Next, hot carrier stress-induced drain leakage current degradation in both nMOSFET's and pMOSFET's is investigated and characterized. Both interface trap and oxide charge effects are considered. In nMOSFET's, the dependence of drain leakage current on oxide thickness is characterized. Results in our study show that the mechanism of hot carrier stress-induced drain leakage current in thin-gate oxide and thick-gate oxide nMOSFET' is markedly different. In ultra-thin gate oxide nMOSFET's, drain leakage current degradation is attributed mostly to interface trap creation, while in relatively thick oxide devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by accelerated degradation in the second stage caused by oxide charge creation. Furthermore, short gate length pMOSET's with STI structure exhibit a hot electron stress-induced subthreshold current hump. This hump effect shows a strong dependence on gate length and is independent of gate width. Enhanced electron trapping efficiency at the edge of STI is found to be the cause of this phenomenon. A qualitative model is proposed to explain this phenomenon. The subthreshold current hump can increase drain leakage current significantly and imposes a limiting factor in device hot carrier lifetime in short gate length STI pMOSFET's. Finally, enhanced hot carrier degradation in DTMOS operation is observed. The enhanced degradation cannot be simply explained by conventional hot carrier theory. Instead, an Auger recombination assisted electron energy gain mechanism is proposed to explain this phenomenon. In order to further confirm this theory, hot electron gate injection current and hot carrier light emission characterization is performed, which provides evidence that the high-energy tail of channel electrons is enhanced by the application of a positive substrate bias. The drain current and flicker noise degradations are about ten times more serious in the DTMOS than in the conventional MOSFET's. As opposed to the conventional hot carrier degradation, the Auger enhanced degradation exhibits positive temperature dependence. Besides, Auger recombination enhanced hot carrier degradation with stress Vg in the valence-band tunneling regime is also observed. Our result shows that the valence-band tunneling enhanced degradation, as opposed to maximum Ib stress induced degradation, exhibits positive dependence on substrate bias. This phenomenon may cause a severe reliability issue in floating substrate devices (SOI) or positively biased substrate devices (DTMOS). On the other hand, a new hot electron programming technique by taking advantage of the Auger recombination assisted hot electron injection is proposed. This method has been shown to have better programming characteristics and excellent temperature stability.
|Appears in Collections:||Thesis|