Fabrication and Characterization of P type SiGe Raised Source and Drain MOSFET Grown by Ultra HighVacuum Chemical Molecular Epitaxy System
|關鍵字:||矽赭合金;金氧半電晶體;鈷金屬矽化物;選擇性磊晶成長;SiGe alloy;Metal Oxide Semiconductor Feild Effect Transistor (MOSFET);Co -Si-Ge Silicide;Seletive Epitaxy Growth(SEG)|
As the transistors continue to scale down, the characteristics of Co/Si1-xGex junction have received lots of attention because of its potential applications to heterojunction bipolar transistors. We have fabricated Co/Si1-xGex junction using room-temperature and high-temperature (i.e., at 450oC) sputtered Co on top of strained Si0.86Ge0.14 and Si0.91Ge0.09 layers prepared by ultra high vacuum chemical molecular epitaxy (UHVCME). The relative composition of Ge in Ge-rich Si1-zGez precipitate and the solid solution of ternary phase silicide of Co-Si-Ge system were compared between room-temperature and high-temperature sputtered samples. We found that the high-temperature-sputtered and boron-doped samples are more effective in inhibiting lattice relaxation, which would be beneficial for manufacturing metal silicide/Si1-xGex structure devices. Mechanisms were proposed to explain the large difference between the room-temperature and high-temperature sputtered samples. It is believed that the mixed Co-Si-Ge solution on high-temperature-sputtered samples is responsible for the different silicidation behaviors. Strained boron-doped Si1-xGex layers with different Ge mole fractions were selectively deposited by ultra high vacuum chemical molecular epitaxy (UHVCME) to form shallow p+-n junction suitable for raised source/drain metal oxide semiconductor field effect transistor (MOSFET) applications. Detailed electrical characterizations were performed. Our results show that the reverse leakage current could be optimized by a rapid thermal annealing (RTA) at 950oC for 20 seconds, and a near perfect forward ideality factor (i.e. < 1.01) is obtained for the p+-n Si1-xGex/Si junction. By analyzing the periphery and area leakage current components of p+-n Si1-xGex/Si junctions with various perimeter lengths and areas, the degree of misfit dislocations and undercut effect were studied. The specific contact resistance was found to decrease as Ge mole fraction increases. Junction depth measurements also show that the junction depth decreases monotonically with increasing Ge mole fraction. The reduced B diffusion constant is attributed to the increasing Ge gradient in the transition region. P-channel MOS transistors with raised Si1-xGex and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impacts of Si1-xGex and Si epitaxial S/D layer on S/D series resistance and drain current of p-channel transistors were studied. Our result show that the new device with Si1-xGex raised S/D layer depicts only half the value of the specific contact resistivity and S/D series resistance (RSD), compared to the device with Si raised S/D layer. The improvement is even more dramatic, when comparing to the conventional device without any raised S/D layer, i.e., RSD of the new device with Si1-xGex raised S/D is only about one fourth the value of the conventional device. Moreover, the device with raised SiGe S/D structure produces a 29% improvement in transconductance (gm) at an effective channel length of 0.16 mm. In addition, Well-behaved short channel characteristics with reduced drain-induced barrier lowering (DIBL) and off-state leakage current are demonstrated on devices with 100nm Si1-xGex RSD, due to the resultant shallow junction and less implantation damage. Moreover, temperature measurements reveal that Si1-xGex RSD devices show more dramatic improvement in device performance at low temperature (-50oC) operation, which can be ascribed to the higher temperature sensitivity of the Si1-xGex sheet resistance. These performance improvements, together with several inherent advantages such as self-aligned selective epitaxial growth (SEG) nature and the resultant T-shaped gate structure, make the new device with raised Si1-xGex S/D structure very attractive for future sub-0.1mm p-channel MOS transistors.
|Appears in Collections:||Thesis|