標題: 高介電係數材料鈦酸鍶鋇Ba0.55Sr0.45TiO3和鐵電材料鈦酸鍶鉛Pb0.6Sr0.4TiO3應用於動態隨機存取記憶體及非揮發性記憶體元件之研究
The Study of High Dielectric-Constant Barium Strontium Titanate (Ba0.55Sr0.45TiO3) and Ferroelectric Lead Strontium Titanate (Pb0.6Sr0.4TiO3) for Giga-Bit DRAM and NVFRAM Storage Capacitor Applications
作者: 莊朝凱
Chao-Kai Chuang
邱碧秀
Dr. Bi-Shiou Chiou
電子研究所
關鍵字: 動態隨機存取記憶體;非揮發性記憶體;DRAM;NVFRAM
公開日期: 1999
摘要: 在本論文中,將針對高介電材料及鐵電材料此兩種材料於動態隨機存取記憶體及非揮發性記憶體作一深入之研究。第一個主題即是高介電係數材料鈦酸鍶鋇於動態隨機存取記憶體電容器的探討;另一則是鐵電材料鈦酸鍶鉛於非揮發性記憶體電容器之研究。茲分述如下: 在動態隨機存取記憶體方面,隨著積體電路密度的增加與元件尺寸的縮小,動態隨機存取記憶體的電容面積與操作電壓亦隨之減小,但為了維持一定的訊號/雜訊比而不產生錯誤的判讀,其所儲存的電荷必須保持一臨界值,因此,我們需要高介電係數材料來保持較簡單結構的記憶單胞,而鈦酸鍶鋇則是下一世代記憶體最備受注意的材料之一,其提供了下列優點:高介電常數、低漏電流、長使用週期、優良的化性、熱穩定性及低損耗因子等。因此對於此一薄膜在動態隨機存取記憶體應用上,本研究則著重在於鈦酸鍶鋇/底電極白金/擴散阻擋層此種結構與矽基板記憶體電路之整合;而其中所選用的三種擴散阻擋層分別為氮化鎢、氮化鉭及氮化矽化鉭,由實驗結果可得知,氮化矽化鉭則是能在高溫下成功地阻擋從介電層來的氧原子擴散至擴散阻擋層之最佳材料,因此,利用一射頻磁控濺鍍系統搭配在白金/氮化矽化鉭/矽基板的結構,成功地沈積具有高介電常數(k>350),及低漏電(~ 10E-8A/cm2)的鈦酸鍶鋇薄膜,並針對不同之薄膜沈積條件,研究其薄膜電性與物性,並加以分析了解其物理機制。 在非揮發性記憶體方面,由於可電性擦拭且可程式唯讀記憶體其讀寫速度較慢,且損耗功率較大,而鐵電隨機存取記憶體則涵蓋多種記憶體的優點,包括擁有靜態隨機存取記憶體的快速讀寫能力,可電性擦拭且可程式唯讀記憶體的非揮發特性,低功率損耗以及長時間讀寫耐久度等,因此鐵電隨機存取記憶體將更適合應用於非揮發記憶體上。而在鐵電性材料中,則以鈦酸鍶鉛為最有潛力的材料之一,因其擁有比一般鐵電性材料還大的殘存極化值。在此論文中,我們首度以極低的基板溫度(300℃)成功地用脈衝雷射濺鍍法(KrF,λ=248nm)成長鐵電薄膜於白金/二氧化矽/矽基板上,並且鐵電薄膜在經過十分鐘、300℃及大氣壓力之氧氣氛的熱處理後,其殘存極化值更可高達30μC/cm2 且矯頑電場亦為45 kV/cm之理想值,另外在經過10E10次的讀寫操作之後仍能維持基本特性,綜上所述,此一低溫薄膜製程將是相當符合鐵電薄膜整合於矽基板非揮發性記憶體上之應用且具有其實用價值。
In this thesis, both DRAM and Non-volatile memory applications of high dielectric-constant and ferroelectric materials have been studied. The first topic focuses on the high dielectric-constant barium strontium titanate (BST) for Giga-bit scale DRAM storage capacitor applications. The second topic is the ferroelectric lead strontium titanate (PST) thin films for NVFRAM storage capacitor applications. The results are described as follows. For DRAM capacitors, with increasing the density of devices on ULSI, the cell areas and applied voltage are rapidly shrinking, which lead to lower storage capacitance while the minimum value of capacitance should be maintained in order to achieve a reasonable signal-to-noise (S/N) ratio. Therefore, High dielectric constant materials are needed to keep a simpler cell structure. The BST is one of the most promising materials due to its high dielectric constant, low leakage current, a TDDB over 10 years and low dissipation factor for high density DRAM capacitor. In this work, the integration of BST thin films with Pt and different barrier on Si-based ICs as DRAM capacitors is the most important issue. The three different barrier layer studied in this work are WN、TaN and TaSiN. From the experimental results, TaSiN was the most appropriate barrier layer to prevent the diffusion of oxygen from the dielectric layer to the barrier electrode even at high temperature process. A high dielectric constant (k=358) and low leakage current (~7x10E-8A/cm2) BST thin film was successfully deposited on Pt/TaSiN/Si substrate by utilizing a RF magnetron sputtering system. The electrical and physical properties of BST films deposited with different deposition parameters were also investigated in order to realize the associated mechanisms. For NVFRAM applications, Ferroelectric random access memories (FRAM memories) combine the features of several different types of memory to offer a true system memory solution. They integrate the fast reads and writes of SRAM, the nonvolatility of EEPROM, low power consumption and very high read/write endurance onto a single, cost effective chip. Among the ferroelectric materials, the PST is one potential candidate material for NVFRAM applications due to its large and reversible remanent polarization characteristics. In this work, the very low temperature (300℃) ferroelectric PST thin films growth was successfully achieved by Pulsed Laser Ablation(KrF,λ=248nm). The remanent polarization and coercive field of PST thin film capacitors after in-situ heat treatment at (300℃)for 10min in O2 atmosphere were about 30 μC/cm2 and 45 kV/cm, respectively. In addition to excellent reliability, thin films properties are maintained even after 10E10 switching cycles. Therefore, this Low temperature Process for ferroelectric thin films is consistent with the integration of ferroelectric thin films with Si-based ICs as FRAM capacitors.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT880428078
http://hdl.handle.net/11536/65718
Appears in Collections:Thesis