標題: 晶圓尺寸記憶體的配置與繞線
On Placement and Routing of Wafer Scale Memory
作者: 張又文
Yoh-Wen Chang
周景揚
Dr. Jing-Yang Jou
電子研究所
關鍵字: 高容量記憶體;晶圓層次;記憶體模組層次;延遲模型;配置;繞線;high capacity memory;wafer level;memory module level;delay model;placement;routing
公開日期: 1999
摘要: 電腦的進步觸發了高容量記憶體的需求。在這篇論文中,我們在晶圓的層次提出了一個創新的配置與繞線方法,用來得到一種相較於目前所使用的記憶體模組而言,具有更大容量以及更好效能的記憶體模組。我們提出了一個記憶體模組層次的時間延遲模型,用來計算金屬連線時間延遲。更進一步地,我們將配置的問題以一個雙邊配合的問題來當做模型,並且將最差狀況的時間延遲做最小化。在完成配置的步驟之後,我們應用一個階層式的繞線方法來產生繞線以及雷射切割的資料。
The progress of computers triggers the requirement of high capacity memory. In this thesis, we propose a novel placement and routing approach at the wafer level to obtain memory modules of larger capacity and with better performance than modern memory modules. We present a delay model at the memory module level to calculate the delay of metal connection. Further, we model the placement problem as a bipartite matching problem, which minimizes the worst case delay. After placement, we apply a hierarchical routing method to generate routing and laser cutting data. ABSTRACT ii ACKNOWLEDGEMENTS iii CONTENTS iv LIST OF TABLES vi LIST OF FIGURES vii Chapter 1 INTRODUCTION………………………… 1 Chapter 2 WAFER SCALE MEMORY………………… 3 2.1 SDRAM structure………………………………… 3 2.2 Wafer Scale Memory Structure……………… 4 2.3 Our Objective…………………………………… 6 2.4 Wafer Scale Memory Architecture…………… 7 Chapter 3 Placement……………………………… 10 3.1 Problem Definition……………………………… 10 3.2 Delay model……………………………………… 11 3.3 Branch and Bound Algorithm…………………… 17 Chapter 4 Routing………………………………… 20 4.1 Special Manufacturing Process………………… 20 4.1.1 Extra Metal layer………………………………… 21 4.1.2 Laser Cutting……………………………………… 21 4.2 Module level Routing…………………………… 22 4.2.1 Clock Routing…………………………………… 22 4.2.2 CS Routing………………………………………… 25 4.2.3 DQ, DQM Routing…………………………………… 27 4.2.4 Other Control Signal and Power Line Routing 28 4.3 Chip Level Routing……………………………… 29 4.3.1 CS Routing………………………………………… 29 4.3.2 DQ, DQM Routing………………………………… 30 4.3.3 Other Control Signals and Power Line Routing 32 4.4 Implementation…………………………………… 32 Chapter 5 Experimental Results………………… 35 Chapter 6 Conclusion……………………………… 40 Chapter 7 Future Work……………………………… 41 7.1 Extended Architecture…………………………… 41 7.2 Comparison of Two Architectures……………… 42 References……………………………………………………… 43
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT880428049
http://hdl.handle.net/11536/65686
Appears in Collections:Thesis