標題: 三維電腦繪圖中非等向性材質貼圖單元之設計Design of An Anisotropic Texture Filtering Processor for 3D Graphics 作者: 劉鴻達Hong-Tar Liu李鎮宜Dr. Chen-Yi Lee電子研究所 關鍵字: 非等向性;紋理材質貼圖;材質像素;內插;透視圖法;取樣;內積;解晰度階層;anisotropic;texture;texel;interpolation;perspective;sample;cross-product;LOD 公開日期: 1999 摘要: 摘 要 在三維電腦繪圖領域中，常使用角錐狀的貼圖對應法來增加三維物件的真實感。在這種角錐貼圖對應法中，細部貼圖階層的選擇往往會影響最後內插求物件成色的誤差。細部貼圖階層的選取將會影響到畫質的巨觀面；相對地，微觀處則由非等向性貼圖濾波來決定。採用較好的形狀或較近似的面積大小理應會得到較佳的線性內插係數，甚至連細部貼圖階層也會更精確。而因一般所使用的皆為等向性內插法，故並不足以生動描繪出一些三維場景中的變形物件。除外，由於非等向性內插法包含了不只一層的細部貼圖階層，往往能有效地減小經由內插所產生的誤差，並獲得較佳的影像品質。 在本篇論文中，將對產生各種細部貼階層的演算法做逐一的探討比較，同時針對一般的低通濾波內插提出修正，並嘗試以不增加取樣像素及硬體頻寬，僅用不同加權內插出近似非等向性貼圖的效果，求取更好的視覺效果。 同時希望這個演算法能在硬體方面加以實踐。因此，本篇論文中也將硬體的架構加以分析，並藉由我們所設計的特殊運算單元來降低硬體複雜度，並且以管線化的設計提高運算速度及效能，再經運算式的化簡、資源的共享來降低硬體成本。整個架構希望能符合可重複使用之矽智產的設計，以求日後整體系統整合之用。Abstract Texture Mapping usually adopts the pyramidal coding makes the object more realistic in domain of 3-D graphics. In pyramidal coding, the key points are the selection of detailed level and the reduction of interpolation error. The appropriate level of detail would make macro impression, in opposition to the micro effect of anisotropic texture filtering. Here, the better approached shape and size will result in more precise linear faction, and even the accurate level of detail. This is usually accomplished through well-designed nonlinear interpolation filters, and those filters are usually isotropic, hence can't account for the anisotropic nature of the 3-D scene. Besides, the anisotropic filter performs interpolation between different detailed levels, implying that the smaller interpolation error would be expected if the anisotropic algorithm is designed well, and hence more realistic and high-quality texture mapping results can be obtained too. In this thesis, we aims at the selection of mip-map texture levels and the algorithms of anisotropic texture filter for 3-D graphics to improve the rendering scene quality. We want to generate the better results for vision without increasing sample numbers and bandwidth only using the modified anisotropic weighted interpolation algorithm. The efficiency of hardware architecture for the proposed algorithms is also taken into account. With our special operation unit, the hardware complexity can be decreased. To enhance rendering speed and throughput, the fully pipelined architecture is designed. By analyzing data flows and operations, many resources sharing techniques can be utilized to reduce hardware cost. The whole architecture tries to fit in with the requirement of reusable IP (Intellectual Property) for system integration easily in future. INTRODUCTION 1.1 INTRODUCTION TO 3D COMPUTER GRAPHICS 1.2 MOVITATION 1.3 OUTLINE OF THE THESIS CHAPTER 2 OVERVIEW OF COMPUTER GRAPHICS 2.1 RENDERING METHODS 2.1.1 Geometric Engine 2.1.2 Vertex Transformation 2.1.3 Perspective Projection 2.1.4 Viewport Transformation 2.1.5 Texture Mapping 2.1.6 Perspective Texture Mapping 2.2 APPLICATION PROGRAMMING INTERFACE 2.2.1 OpenGL 2.2.2 DirectX 2.3 ACCELERATION HARDWARE 2.3.1 InfiniteReality Architecture 2.3.2 Talisman Architecture 2.3.3 3D Computer Graphics Bottlenecks CHAPTER 3 3D GRAPHICS PERSPECTIVE TEXTURE MIP-MAP PROCESS 3.1 MIP-MAP TEXTURE MAPPING 3.2 APPROXIMATION TECHNIQUES FOR TEXTURE MAPPING 3.2.1 Geometric Transformation 3.2.2 Calculate Texture Minification 3.3 SIMULATION RESULT 3.4 SAMPLING AND FILTER METHOD CHAPTER 4 ANISOTROPIC INTERPOLATION ALGORITHM 4.1 FOOTPRINT ASSEMBLY 4.1.1 Talisman Anisotropic Filtering Process 4.1.2 Texram: Anisotropic Filtering Process 4.1.3 Summary 4.2 RECONSTRUCT MIP-MAP TEXTURE 4.3 ANISOTROPIC INTERPOLATION 4.3.1 Bilinear and Trilinear Interpolation 4.3.2 Direct address of the four pixel corners & center 4.3.3 Hypotenuse weighting interpolation 4.3.4 Anisotropic interpolation 4.3.5 Modified anisotropic weighted interpolation 4.3.6 Summary 4.3.7 Simulation Results and Discussion CHAPTER 5 HARDWARE ARCHITECTURE 5.1 SYSTEM REQUIREMENT 5.2 DESIGN SPECIFICATION 5.2.1 Pipeline stages and numerical precision 5.2.2 Texture span setup 5.2.3 The Reciprocal Unit 5.2.4 LOD and Texture coordinate generation 5.2.5 The Log Operator 5.2.6 Sampling and Filtering 5.3 MEMORY LOCATION CONTROLLER 5.4 PERFORMANCE ANALYSIS 5.5 VERIFICATION 5.6 IP-BASED DESIGN 5.6.1 The Reciprocal Unit 5.6.2 The Log Operator Unit 5.6.3 Memory Location Controller 5.6.4 Various Filtering Mode CHAPTER 6 CONCLUSIONS AND FUTURE WORKS 6.1 CONCLUSIONS 6.2 FUTURE WORKS BIBLIOGRAPHY APPENDIX A THE CHIP OF 3D ACCELERATION GRAPHICS IN MARKET URI: http://140.113.39.130/cdrfb3/record/nctu/#NT880428040http://hdl.handle.net/11536/65676 Appears in Collections: Thesis