DC FieldValueLanguage
dc.contributor.author鍾興明en_US
dc.contributor.authorHsin-Ming Chungen_US
dc.contributor.author陳伯寧en_US
dc.contributor.authorPo-Ning Chenen_US
dc.date.accessioned2014-12-12T02:21:00Z-
dc.date.available2014-12-12T02:21:00Z-
dc.date.issued1998en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT870435047en_US
dc.identifier.urihttp://hdl.handle.net/11536/64506-
dc.description.abstract維特比 (Viterbi) 演算法雖然是最大概度解碼演算法, 但是它只有在較短的固定長度(constraint length)時才能實現. 序列解碼 (Sequential decoding) 演算法的複雜度雖然和固定長度無關, 但是它不能達到最大可靠度決策. 韓教授和陳教授提出的最大可靠度序列解碼演算法 (MLSDA) 不但具有序列解碼的優點, 同時它也是最大可靠度解碼演算法. 根據最大可靠度序列解碼演算法, 我們做解碼器的實作探討. 一般傳統的序列解碼搜尋方法是把所有資料放在記憶體中直接做排列, 而每次所須時間則視資料多寡而定. 為了維持固定的排序時間, 我們修正了優先排隊演算法 (PESPQ) 來實現最大可靠度序列解碼演算法. 這種作法雖然會增加設計的複雜度, 但是可以保證在固定時間內能得到最好的結果. 我們也提出一個序列解碼的觀點, 將1/2碼視為2/4碼 (3/6碼), 即是在解碼的過程中結合二 (三) 個輸入位元成一個單位. 因此我們可以在VLSI的實作上得到一些好處例如解碼速度, 但是也相對的增加半導體的數目. 為了減少半導體的數目, 我們使用多輸入躍動排序演算法來完成2/4碼 (3/6碼) 的MLSDA. 根據模擬結果, 當半導體數量增加一半時解碼速度可以增加一倍.zh_TW
dc.description.abstractViterbi algorithm is a maximum-likelihood-decoding algorithm, but it can only be implemented in short constraint length. Sequential decoding decoding is independent of constraint length but the decoding result is not always a maximum-likelihood decision. The MLSDA proposed by Han and Chen has the advantage of sequential decoding and it is also a maximum-likelihood-decoding algorithm. According to MLSDA, we implement a new convolutional code decoder using stacks. The tranditional method for sorting the nodes serached in the sequential decoding is using a RAM to model a stack memory, and the sorting time is not a constant duration. In order to fix this shortage, we modify the priority queue algorithms (PESPQ) to implement MLSDA. Although the priority queue module is more complex than the stack memory, it can deliver the best node in a constant duration. All 1/2 convolutional codes may be treated as an equivalent 2/4 (3/6) codes during the decoding phase if we combine two (three) input bits as one unit. Consequently, we might have some advantage in VLSI implementation such as decoding speed; however, the gate counts of decoder will be increased. In order to reduce the number of gate counts we modify a multiple-inputs systolic queue algorithm to implement MLSDA for 2/4 (3/6) codes. As the simulation shown, the decoding speed may be double faster for (2/4) while the gate counts increase half.en_US
dc.language.isozh_TWen_US
dc.subject序列解碼zh_TW
dc.subject律動矩陣zh_TW
dc.subjectsequential decodingen_US
dc.title最大概度軟性決策序列解碼之律動矩陣架構實作探討zh_TW
dc.titleA systolic-array implementation of maximum-likelihood soft-decision sequential decodingen_US
dc.typeThesisen_US
dc.contributor.department電信工程研究所zh_TW
Appears in Collections:Thesis