標題: Electrical characteristics dependence on the channel fin aspect ratio of multi-fin field effect transistors
作者: Cheng, Hui-Wen
Li, Yiming
傳播研究所
電子工程學系及電子研究所
Institute of Communication Studies
Department of Electronics Engineering and Institute of Electronics
公開日期: 2-十一月-2009
摘要: In this work we investigate the impact of the fin number and structure on device dc and dynamic behaviors of multi-fin field effect transistor (FET) circuits. Based on the same channel volume, multi-fin FETs with different fin aspect ratio (AR equivalent to fin height/fin width) are explored using an experimentally validated three-dimensional device simulation. The multi-fin FinFET (AR = 2) has a better channel controllability than the tri-gate (AR = 1) and the quasi-planar (AR = 0.5) FETs. Besides, the 6T SRAM with triple-fin FinFETs provides the largest static noise margin because of the largest transconductance. Notably, though the FinFETs are with a large effective fin width and driving current, the larger gate capacitance may limit the intrinsic device gate delay. The transient characteristics of multi-fin inverters are further examined with different load capacitance (C(load)). As C(load) is increased, the impact of the device intrinsic gate capacitance on transient characteristcs is decreased and the delay time compared with that of single-fin inverters is smaller due to being dominated by the driving current of the transistor. Consequently, the multi-fin FinFET circuits exhibit a smallest delay time. The results of the study provide an insight into the dc and transient characteristics of multi-fin transistors and associated digital circuits.
URI: http://dx.doi.org/10.1088/0268-1242/24/11/115021
http://hdl.handle.net/11536/6447
ISSN: 0268-1242
DOI: 10.1088/0268-1242/24/11/115021
期刊: SEMICONDUCTOR SCIENCE AND TECHNOLOGY
Volume: 24
Issue: 11
結束頁: 
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